S i535 5
A
N Y
-F
R E Q U E N C Y
1–20 0 MH
Z
Q
U A D
F
R E Q U E N C Y
8-O
U T P U T
C
L O C K
G
E N E R A T O R
Features
Generates any frequency from 1 to
200 MHz on each of the 4 output banks
Eight CMOS clock outputs
Guaranteed 0 ppm frequency synthesis
error for any combination of frequencies
25 or 27 MHz xtal or 5–200 MHz input clk
Five programmable control pins (output
enable, frequency select, reset)
Separate OEB pins to disable individual
banks or all outputs
Loss of signal output
Low 50 ps (typ) pk-pk period jitter
Phase jitter: 2 ps rms 12 kHz–20 MHz
Excellent PSRR performance
eliminates need for external power
supply filtering
Low power: 45 mA (core)
Core VDD: 1.8, 2.5, or 3.3 V
Separate VDDO for each bank of
outputs: 1.8, 2.5, or 3.3 V
Small size: 4x4 mm 24-QFN
Industrial temperature range:
–40 to +85 °C
Custom versions available using
ClockBuilder™ web utility
Samples available in 2 weeks
Ordering Information:
See page 17.
Pin Assignments
Applications
Printers
Audio/video
Networking
Communications
Storage
Switches/routers
Computing
Servers
OC-3/OC-12 line cards
Description
The Si5355 is a highly flexible clock generator capable of synthesizing four
completely non-integer related frequencies up to 200 MHz. The device has four
banks of outputs with each bank supporting two CMOS outputs at the same
frequency. Using Silicon Laboratories' patented MultiSynth fractional divider
technology, all outputs are guaranteed to have 0 ppm frequency synthesis error
regardless of configuration, enabling the replacement of multiple clock ICs and
crystal oscillators with a single device. Through a flexible web configuration utility
called ClockBuilder™ (www.silabs.com/ClockBuilder), factory-customized pin-
controlled Si5355 devices are available in two weeks without minimum order
quantity restrictions. The Si5355 supports up to three independent, pin-selectable
device configurations, enabling one device to replace three separate clock ICs.
Functional Block Diagram
Rev. 1.2 4/17
Copyright © 2017 by Silicon Laboratories
Si5355
Si5355
T
A B L E
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2. Breakthrough MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3. Input and Output Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4. Multi-Function Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.6. Frequency Select/Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.7. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.8. CMOS Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.9. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.10. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.11. ClockBuilder Web-Customization Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.1. Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
8.1. Si5355 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.2
3
Si5355
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Core Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
2.97
2.25
1.71
Typ
—
3.3
2.5
1.8
—
Max
85
3.63
2.75
1.98
3.63
Units
o
C
V
Output Buffer Supply Voltage
V
DDO
1.71
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating
conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless
otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
Output Buffer Supply Current
Symbol
I
DD
I
DDOx
Test Condition
100 MHz on all outputs,
25 MHz refclk
CMOS, 50 MHz
15 pF load
CMOS, 200 MHz
3.3 V VDD0
CMOS, 200 MHz
2.5 V
CMOS, 200 MHz
1.8 V
Min
—
—
—
—
—
0.8 x V
DD
0.85
1.6
–0.2
—
V
DDO
– 0.3
—
0
—
Typ
45
6
13
10
7
—
—
—
—
—
—
—
—
20
Max
60
9
18
14
10
3.63
1.3
3.63
0.2 x V
DD
0.3
—
0.3
0.4
—
Units
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
k
High Level Input Voltage
V
IH
CLKIN, P1
P4, P5
P2, P3
Low Level Input Voltage
Clock Output High Level Output
Voltage
Clock Output Low Level Out-
put Voltage
LOS Low Level Output Voltage
Pn Input Resistance
V
IL
V
OH
V
OL
V
OLLOS
R
IN
CLKIN, P1, P2, P3
P4,P5
Pins: CLK0-7
I
OH
= –4 mA
Pins: CLK0-7
I
OL
= +4 mA
Pin: LOS
I
OL
= +3 mA
4
Rev. 1.2
Si5355
Table 3. AC Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Input Clock
Clock Input Frequency
Clock Input Rise/Fall Time
Clock Input Duty Cycle
Clock Input Capacitance
Output Clocks
Clock Output Frequency
Clock Output Frequency Synthesis
Resolution
Output Load Capacitance
Clock Output Rise/Fall Time
Clock Output Rise/Fall Time
Clock Output Duty Cycle
Powerup Time
Output Enable Time
Reset Minimum Pulse Width
Output-Output Skew
Period Jitter
Cycle-Cycle Jitter*
Phase Jitter
PLL Loop Bandwidth
Interrupt Status Timing
CLKIN Loss of Signal Assert Time
CLKIN Loss of Signal Deassert
Time
LOS Rise/Fall Time (20–80%)
Symbol
F
IN
T
R
/T
F
DC
C
IN
F
O
F
RES
Test Condition
Min
5
Typ
—
—
—
—
2
—
0
Max
200
2.3
4
60
—
200
1
Units
MHz
ns
ns
%
pF
MHz
ppb
20–80% V
DD
10–90% V
DD
Input tr/tf within specified
limits shown above
—
—
40
—
1
See "3.3. Input and Output
Frequency Configuration"
on page 10
20 to 80% V
DD
,
C
L
= 15 pF
20 to 80% V
DD
,
C
L
= 2 pF
POR to output clock valid
0
C
L
T
R
/T
F
T
R
/T
F
DC
T
PU
T
OEB
T
RESET
T
SKEW
J
PPKPK
J
CCPK
J
PH
F
BW
t
LOS
t
LOS_b
T
R
/T
F
C
L
< 10 pF, pullup < 1 k
Outputs at same
frequency, f
OUT
> 5 MHz
10000 cycles*
10000 cycles*
12 kHz to 20 MHz
—
—
—
45
—
—
—
–150
—
—
—
—
—
0.01
—
—
—
0.45
50
—
—
—
—
50
40
2
1.6
2.6
0.2
—
15
2.0
0.85
55
2
10
200
+150
75
70
—
—
5
1
10
pF
ns
ns
%
ms
μs
ns
ps
ps pk-pk
ps pk
ps rms
MHz
μs
μs
ns
*Note:
Measured in accordance to JEDEC Standard 65.
Rev. 1.2
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
