Integrated random phase jitter (RMS, 12kHz-20MHz): 0.51ps
Phase Noise (dBc/Hz)
10
4
10
10
Frequency Offset (Hz)
5
6
10
7
Rev. 1.0
Page 3 of 6
www.sitime.com
SiT5002
80-220 MHz MEMS TCXO and VCTCXO
The Smart Timing Choice
The Smart Timing Choice
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
[3]
2.7 x 2.4 x 0.75 mm (100% compatible with 2.5 x 2. 0 mm footprint)
Recommended Land Pattern (Unit: mm)
[4]
YXXXX
3.2 x 2.5 x 0.75 mm
2.2
#4
3.2 ± 0.05
#4
#3
#3
2.1
2.5 ± 0.05
0.9
0.7
YXXXX
#1
#2
1.9
#2
#1
0.75 ± 0.05
0.9
1.4
5.0 x 3.2 x 0.75 mm
2.54
5.0 ± 0.05
#4
#3
#3
2.39
#4
3.2 ± 0.05
0.8
1.1
YXXXX
#1
#2
2.2
0.75 ± 0.05
#2
#1
1.15
1.5
7.0 x 5.0 x 0.90 mm
7.0 ± 0.05
5.08
5.08
5.0 ± 0.05
2.6
YXXXX
1.1
3.81
0.90 ± 0.10
1.4
2.2
Notes:
3. Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.
4. A capacitor of value 0.1
F
between Vdd and GND is recommended.
Rev. 1.0
Page 4 of 6
2.0
1.6
1.2
www.sitime.com
SiT5002
80-220 MHz MEMS TCXO and VCTCXO
The Smart Timing Choice
The Smart Timing Choice
Ordering Information
The Part No. Guide is for reference only. To customize and build an exact part number, use the SiTime
Part Number
Generator.
SiT5002AC -2E-18VQ-1 5 5.520000T
Packaging
Part Family
SiT5002
Revision Letter
“A” is the revision
Temperature Range
“C” Commercial, -20 to 70ºC
“I” Industrial, -40 to 85ºC
Output Waveform
“-“ Default
[5]
Frequency
80.000001 to 220.000000 MHz
“0” for fixed frequency
(Pin1 = “E”, “S” or “N” options)
Pull Range Options
(Pin1 = “V” option only)
“Q” for ±12.5 ppm
“M” for ±25 ppm
“B” for ±50 ppm
Feature Pin (pin 1)
“V” for Voltage Control
“E” for Output Enable
“S” for Standby
“N” for No Connect
Supply Voltage
“18” for 1.8 V ±5%
“25” for 2.5 V ±10%
“28” for 2.8 V ±10%
“30” for 3.0 V ±10%
“33” for 3.3 V ±10%
“T”: Tape & Reel, 3K reel
“Y”: Tape & Reel, 1K reel
Blank for Bulk
Package Size
“G”
“2”
“3”
“8”
2.5 x 2.0 mm
3.2 x 2.5 mm
5.0 x 3.2 mm
7.0 x 5.0 mm
Frequency Stability
[6]
“E” for ±5 ppm
Notes:
5. SiTime’s SoftEdge™ output waveform with 6 ns rise/fall time reduces EMI and is similar to clipped sine wave in functionality.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
