PRELIMINARY
MX29F080
8M-BIT [1024K x 8] CMOS EQUAL SECTOR FLASH MEMORY
FEATURES
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1,048,576 x 8 byte mode only
Single power supply operation
- 5.0V only operation for read, erase and program
operation
Fast access time: 70/90/120ns
Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
Command register architecture
- Byte Programming (7us typical)
- Sector Erase of 16 equal sector with 64K-Byte each
Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, another sector that is not being
erased, then resumes the erase.
•
Status Reply
- Data polling & Toggle bit for detection of program
and erase operation completion.
Ready/Busy (RY/BY)
- Provides a hardware method of detecting program
and erase operation completion.
Sector Group protect/chip unprotect for 5V/12V sys-
tem.
Sector Group protection
- Hardware protect method for each group which con-
sists of two adjacent sectors
- Temporary sector group unprotect allows code
changes in previously locked sectors
10,000 minimum erase/program cycles
Latch-up protected to 100mA from -1V to VCC+1V
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 40-pin TSOP or 44-pin SOP
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
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GENERAL DESCRIPTION
The MX29F080 is a 8-mega bit Flash memory organized
as 1024K bytes of 8 bits. MXIC's Flash memories offer
the most cost-effective and reliable read/write non-vola-
tile random access memory. The MX29F080 is pack-
aged in 40-pin TSOP or 44-pin SOP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29F080 offers access time as fast as
70ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F080 has separate chip enable (CE) and output
enable (OE ) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F080 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 10,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
cycling. The MX29F080 uses a 5.0V±10% VCC supply
to perform the High Reliability Erase and auto Program/
Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0579
REV. 1.6, NOV, 21, 2002
1
MX29F080
PIN CONFIGURATIONS
40 TSOP (Standard Type) (10mm x 20mm)
20
A0-A19
A19
A18
A17
A16
A15
A14
A13
A12
CE
VCC
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE
OE
RY/BY
Q7
Q6
Q5
Q4
VCC
VSS
VSS
Q3
Q2
Q1
Q0
A0
A1
A2
A3
LOGIC SYMBOL
8
Q0-Q7
CE
OE
WE
RESET
RY/BY
MX29F080
44 SOP
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
Q0
Q1
Q2
Q3
VSS
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE
OE
RY/BY
Q7
Q6
Q5
Q4
VCC
PIN DESCRIPTION
SYMBOL
A0~A19
Q0~Q7
CE
WE
OE
RESET
RY/BY
VCC
VSS
NC
PIN NAME
Address Input
8 Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Hardware Reset Pin, Active Low
Read/Busy Output
+5.0V single power supply
Device Ground
Pin Not Connected Internally
P/N:PM0579
MX29F080
REV. 1.6, NOV. 21, 2002
2
MX29F080
SECTOR STRUCTURE
MX29F080 SECTOR ADDRESS TABLE
Sector Group
SGA0
SGA0
SGA1
SGA1
SGA2
SGA2
SGA3
SGA3
SGA4
SGA4
SGA5
SGA5
SGA6
SGA6
SGA7
SGA7
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address Range
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
Legend:SA=Sector Address ;
SGA
=Sector Group Address
Note:All sectors are 64 Kbytes in size.
P/N:PM0579
REV. 1.6, NOV. 21, 2002
3
MX29F080
BLOCK DIAGRAM
WRITE
CE
OE
WE
CONTROL
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
PROGRAM/ERASE
STATE
X-DECODER
MX29F080
FLASH
ARRAY
ARRAY
STATE
REGISTER
ADDRESS
LATCH
A0-A19
AND
BUFFER
SENSE
AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
P/N:PM0579
REV. 1.6, NOV. 21, 2002
4
MX29F080
AUTOMATIC PROGRAMMING
The MX29F080 is byte programmable using the Auto-
matic Programming algorithm. The Automatic Program-
ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro-
grammed. The typical chip programming time at room
temperature of the MX29F080 is less than 8 seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, re-
liability, and cost effectiveness. The MX29F080 electri-
cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed by using
the EPROM programming mechanism of hot electron
injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 8 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29F080 is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes
allow sectors of the array to be erased in one erase
cycle. The Automatic Sector Erase algorithm
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation.
P/N:PM0579
REV. 1.6, NOV. 21, 2002
5
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