MX29LV002C/002NC T/B
2M-BIT [256K x 8] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 262,411 x 8
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 70/90ns
• Low power consumption
- 20mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte Programming (9us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x3)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
- Data# Polling & Toggle bit for detection of program
and erase operation completion.
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or
erase operation completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors
• CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Hardware RESET# pin (only for 29LV002C)
- Resets internal state machine to read mode
• Package type:
- 32-pin TSOP (type 1)
- 32-pin PLCC
• 20 years data retention
GENERAL DESCRIPTION
The MX29LV002C T/B is a 2-mega bit Flash memory
organized as 256K bytes of 8 bits. MXIC's Flash memo-
ries offer the most cost-effective and reliable read/write
non-volatile random access memory. The MX29LV002C
T/B is packaged in 32-pin TSOP and 32-pin PLCC. It is
designed to be reprogrammed and erased in system or
in standard EPROM programmers.
The standard MX29LV002C T/B offers access time as
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV002C T/B has separate chip enable
(CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV002C T/B uses a command register to manage
this functionality. The command register allows for 100%
P/N:PM1204
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV002C T/B uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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MX29LV002C/002NC T/B
PIN CONFIGURATIONS
32 TSOP (TYPE 1)
A11
A9
A8
A13
A14
A17
WE#
VCC
RESET#
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
32 PLCC
RESET#
A12
A15
A16
NC on MX29LV002NC
WE#
VCC
A7
A6
A5
A4
A3
A2
A1
A0
Q0
5
4
1
32
30
29
A17
A14
A13
A8
MX29LV002C/002NC T/B
MX29LV002C/
9
A9
25
A11
OE#
A10
CE#
002NC T/B
13
14
Q1
Q2
VSS
17
Q3
Q4
Q5
21
20
Q6
Q7
NC on MX29LV002NC
PIN DESCRIPTION
SYMBOL
A0~A17
Q0~Q7
CE#
WE#
RESET#
OE#
VCC
GND
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Hardware Reset Pin/Sector Protect
Unlock
Output Enable Input
Power Supply Pin (+3V)
Ground Pin
SECTOR STRUCTURE
A17~A0
3FFFFH
3BFFFH
8
39FFFH
8
37FFFH
2FFFFH
64
1FFFFH
64
0FFFFH
64
00000H
K-BYTE
K-BYTE
K-BYTE
32
K-BYTE
K-BYTE
K-BYTE
A17~A0
3FFFFH
64
2FFFFH
64
1FFFFH
0FFFFH
07FFFH
05FFFH
03FFFH
00000H
8
8
K-BYTE
K-BYTE
64
32
K-BYTE
K-BYTE
K-BYTE
K-BYTE
16 K-BYTE
(BOOT SECTOR)
16 K-BYTE
(BOOT SECTOR)
MX29LV002CT Sector Architecture
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MX29LV002CB Sector Architecture
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MX29LV002C/002NC T/B
BLOCK DIAGRAM
WRITE
WE#
OE#
WP#
RESET#
CONTROL
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
PROGRAM/ERASE
STATE
X-DECODER
ADDRESS
LATCH
A0~A17
AND
BUFFER
FLASH
ARRAY
ARRAY
STATE
REGISTER
SENSE
AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
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3
MX29LV002C/002NC T/B
AUTOMATIC PROGRAMMING
The MX29LV002C T/B is byte programmable using the
Automatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29LV002C T/B is less than 10
seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# or CE#, whichever
happens first.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29LV002C T/B
electrically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 4 second. The Automatic Erase algorithm au-
tomatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29LV002C T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
sector(s) prior to electrical erase. The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
The device provides an unlock bypass mode with faster
programming. Only two write cycles are needed to pro-
gram a byte, instead of four. A status bit similar to Data#
Polling and a status bit toggling between consecutive
read cycles, provide feedback to the user as to the sta-
tus of the programming operation. Refer to write opera-
tion status, table7, for more information on these status
bits.
AUTOMATIC SELECT
The automatic select mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on Q7~Q0. This mode is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9 and other address pin A6, A1 as referring to Table
3. In addition, to access the automatic select codes in-
system, the host can issue the automatic select com-
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REV. 1.0, JUN. 30, 2005
4
MX29LV002C/002NC T/B
mand through the command register without requiring VID,
as shown in table4.
To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest or-
der address bit (see Table 1 and Table 2). The rest of
address bits, as shown in table3, are don't care. Once
all necessary bits have been set as required, the pro-
gramming equipment may read the corresponding iden-
tifier code on Q7~Q0.
TABLE 3. MX29LV002C T/B AUTOSELECT MODE OPERATION
A17 A12
Description
Manufacture Code
Read
Silicon
ID
Device ID
(Top Boot Block)
Device ID
(Bottom Boot Block)
01H
Sector Protection Verification
L
L
H
H
SA
X
VID
X
L
X
H
L
(protected)
00H
(unprotected)
L
L
H
H
X
X
VID
X
L
X
L
H
5AH
CE# OE# WE# RESET#
L
L
L
L
H
H
H
H
|
X
X
|
X
X
A9
VID
VID
(note) A13 A10
A8
|
A7
X
X
L
L
A6
A5
|
A2
X
X
L
L
L
H
C2H
59H
A1 A0
Q7~Q0
NOTE: SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High.
RESET# pin for 32-TSOP only.
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5
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