HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
Features:
◆
◆
IDT7015S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 12/15/17/20/25/35ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT7015S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
IDT7015 easily expands data bus width to 18 bits or more
using the Master/Slave select when cascading more than
one device
◆
◆
◆
◆
◆
◆
◆
◆
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PLCC and an 80-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
12L
A
0L
(1,2)
I/O
Control
I/O
0R
-I/O
8R
BUSY
R
Address
Decoder
13
(1,2)
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. In MASTER mode:
BUSY
is an output and is a push-pull driver
In SLAVE mode:
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull drivers.
M/S
2954 drw 01
SEM
R
(2)
INT
R
OCTOBER 2017
1
©2017 Integrated Device Technology, Inc.
DSC 2954/12
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT7015 is a high-speed 8K x 9 Dual-Port Static RAM. The
IDT7015 is designed to be used as a stand-alone Dual-Port RAM or as
a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 750mW of power.
The IDT7015 is packaged in a 64-pin PLCC and an 80-pinTQFP
(Thin Quad Flatpack).
Pin Configurations
(1,2,3)
I/O
6R
I/O
5R
I/O
4R
I/O
3R
V
CC
I/O
2R
I/O
1R
I/O
0R
GND
V
CC
I/O
7L
I/O
6L
GND
I/O
5L
I/O
4L
I/O
3L
I/O
2L
I/O
7R
I/O
8R
OE
R
R/W
R
SEM
R
CE
R
N/C
N/C
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
7015
J68
(4)
1
68
67
66
65
64
63
62
43
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
I/O
1L
I/O
0L
I/O
8L
OE
L
R/W
L
SEM
L
CE
L
N/C
N/C
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
2954 drw 02
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
GND
BUSY
L
INT
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
12L
I/O
0L
- I/O
8L
SEM
L
INT
L
BUSY
L
Pin Names
Right Port
CE
R
R/W
R
OE
R
A
0R
- A
12R
I/O
0R
- I/O
8R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2954 tbl 01
Names
6.42
2
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
A
1L
A
0L
INT
L
BUSY
L
BUSY
R
INT
R
GND
M/S
A
0R
A
1R
NC
A
5L
A
4L
A
3L
A
2L
A
2R
A
3R
A
4R
45
44
43
NC
NC
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
V
CC
NC
NC
NC
CE
L
SEM
L
R/W
L
OE
L
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
42
41
40
39
38
37
36
35
34
33
32
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
NC
NC
NC
NC
A
5R
A
6R
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
GND
NC
NC
NC
CE
R
SEM
R
R/W
R
OE
R
7015
PN80
(4)
31
30
29
28
27
26
25
24
23
22
21
I/O
8L
I/O
0L
I/O
1L
I/O
8R
I/O
7R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2954 drw 03
GND
GND
V
CC
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
NC
NC
INDEX
NOTES:
1. All Vcc must be connected to power supply.
2. All GND must be connected to ground supply.
3. PN80 package body is approximately
14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
3
6.42
NC
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-8
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
2954 tbl 02
Mode
NOTE:
1.
Condition: A
0L
— A
12L
=
A
0R
— A
12R
Truth Table II: Semaphore Read/Write CONTROL
(1)
Inputs
(1)
CE
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-8
DATA
OUT
DATA
IN
____
Mode
Read Semaphore Flag Data Out (I/O
0-8
)
Write I/O
0
into Semaphore Flag
Not Allowed
2954 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O
s
(I/O
0
- I/O
8
). These eight semaphores are addressed by A
0
- A
2
.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Maximum Operating
Temperature and Supply Voltage
(1)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
2954 tbl 05
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
Industrial
o
NOTES:
1. This is the parameter T
A
. There is the "instant on" case temperature.
mA
2954 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2954 tbl 06
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
6.42
4
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Capacitance
(1)
Symbol
C
IN
C
OUT
(T
A
= +25°C, f = 1.0mhz, for TQFP Package)
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2954 tbl 07
NOTES:
1. This parameter is determined by device characteristics but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V .
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
7015S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
7015L
Max.
10
10
0.4
___
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2954 tbl 08
2.4
2.4
NOTE:
1. At Vcc < 2.0V, Input leakages are undefined.
Output Loads and
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
(1)
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
2954 tbl 09
5V
893Ω
DATA
OUT
BUSY
INT
347Ω
30pF
DATA
OUT
347Ω
5V
893Ω
5pF
*
2954 drw 05
2954 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For t
LZ
, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig.
5
6.42
Microchip MCU
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