260MHz, Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
General Description
The 84021 is a general purpose, Crystal-to-LVCMOS/LVTTL High
Frequency Synthesizer. The 84021 has a selectable TEST_CLK or
crystal input. The VCO operates at a frequency range of 620MHz to
780MHz. The VCO frequency is programmed in steps equal to the
value of the input reference or crystal frequency. The VCO and
output frequency can be programmed using the serial or parallel
interface to the configuration logic.
84021
DATA SHEET
Features
•
•
•
•
•
•
•
•
Two LVCMOS/LVTTL outputs
Selectable crystal oscillator interface or LVCMOS/LVTTL
TEST_CLK
Output frequency range: 103.3MHz to 260MHz
Crystal input frequency range: 14MHz to 40MHz
VCO range: 620MHz to 780MHz
Parallel or serial interface for programming counter and output
dividers
RMS period jitter: 14.7ps (typical), (N ÷ 4, V
DDO
= 3.3V±5%)
RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz
to 20MHz): 2.61ps (typical)
Offset
Noise Power
100Hz.................-87.9 dBc/Hz
1kHz ...................-115.8 dBc/Hz
10kHz .................-124.2 dBc/Hz
100kHz ...............-127.7 dBc/Hz
•
•
•
•
Full 3.3V or mixed 3.3V core/2.5V or 1.8V output supply voltage
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in lead-free (RoHS 6) package
Block Diagram
OE0
Pullup
OE1
Pullup
VCO_SEL
Pullup
XTAL_SEL
Pullup
TEST_CLK
Pulldown
XTAL_IN
Pin Assignment
VCO_SEL
nP_LOAD
M2
XTAL_IN
M4
M3
M1
M0
32 31 30 29 28 27 26 25
M5
1
2
3
4
5
6
7
8
9
TEST
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
Q1
V
DDO
GND
V
DD
OE1
OE0
Q0
XTAL_OUT
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
0
M6
M7
M8
N0
N1
OSC
XTAL_OUT
1
PLL
nc
GND
Phase Detector
MR
Pulldown
VCO
÷M
0
1
N
÷3
÷4
÷5
÷6
Q0
Q1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
Pulldown
Pulldown
Pulldown
Pulldown
Configuration Interface Logic
TEST
84021
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
M[0:8]
M5 Pullup; M[0:4, 6:8] Pulldown
N[0:1]
Pulldown
84021 Rev E 9/23/15
1
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The 84021 features a fully integrated PLL and therefore requires no
external components for setting the loop bandwidth. A fundamental
crystal is used as the input to the on-chip oscillator. The output of the
oscillator is fed into the phase detector. A 25MHz crystal provides a
25MHz phase detector reference frequency. The VCO of the PLL
operates over a range of 620MHz to 780MHz. The output of the M
divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVCMOS output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the 84021 support two input modes to
program the M divider and N output divider. The two input operational
modes are parallel and serial.
Figure 1
shows the timing diagram for
each mode. In parallel mode, the nP_LOAD input is initially LOW.
The data on inputs M0 through M8 and N0 and N1 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial
event occurs. As a result, the M and N bits can be hardwired to set
the M divider and N output divider to a specific default state that will
automatically occur during power-up. The TEST output is LOW when
operating in the parallel input mode. The relationship between the
VCO frequency, the crystal frequency and the M divider is defined as
follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 25MHz reference are
defined as 25
M
31.
The frequency out is defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_DATA, Shift Register Input
Output of M Divider
CMOS FOUT
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T1
S
T0
*NULL
N1
H
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M[0:8], N[0:1]
nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
*NOTE: The NULL timing slot must be observed.
Figure 1. Parallel & Serial Load Operations
84021 Rev E 9/23/15
2
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
8, 16
9
10
11, 12
13
14, 15
Name
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
GND
TEST
V
DD
OE1, OE0
V
DDO
Q1, Q0
Input
Input
Type
Pullup
Pulldown
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD
input. LVCMOS/LVTTL interface levels.
Determines N output divider value as defined in Table 3C, Function
Table. LVCMOS/LVTTL interface levels.
No connect.
Power supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Pullup
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in an Hi-Z state. See Table 3E, OE
Function Table. LVCMOS/LVTTL interface levels.
Output supply pin.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When Logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not affect
loaded M, N, and T values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pullup
Pulldown
Selects between crystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS/LVTTL interface levels.
Single-ended test clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Pulldown
Parallel load input. Determines when data present at M[8:0] is loaded into
M divider, and when data present at N[1:0] sets the N output divider
value. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
Description
Input
Unused
Power
Output
Power
Input
Power
Output
Pulldown
17
MR
Input
Pulldown
18
19
20
21
22
23
24,
25
26
S_CLOCK
S_DATA
S_LOAD
V
DDA
XTAL_SEL
TEST_CLK
XTAL_OUT
XTAL_IN
nP_LOAD
Input
Input
Input
Power
Input
Input
Input
Pulldown
Pulldown
Pulldown
Input
27
VCO_SEL
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
84021 Rev E 9/23/15
3
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
V
DDO
= 3.465V
C
PD
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
V
DDO
= 3.3V ± 5%
R
OUT
Output Impedance
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 5%
V
DDO
= 2.625V
V
DDO
= 1.89V
R
PULLUP
R
PULLDOWN
Test Conditions
Minimum
Typical
4
15
15
20
51
51
7
7
10
Maximum
Units
pF
pF
pF
pF
k
k
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
L
H
S_CLOCK
X
X
X
L
L
X
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M divider and
N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider and
N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
= Rising edge transition
= Falling edge transition
84021 Rev E 9/23/15
4
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 3B. Programmable VCO Frequency Function Table
(NOTE 1)
VCO Frequency
(MHz)
625
•
700
•
775
256
M Divide
25
•
28
•
31
M8
0
•
0
•
0
128
M7
0
•
0
•
0
64
M6
0
•
0
•
0
32
M5
0
•
0
•
0
16
M4
1
•
1
•
1
8
M3
1
•
1
•
1
4
M2
0
•
1
•
1
2
M1
0
•
0
•
1
1
M0
1
•
0
•
1
NOTE 1: These M divide values and the resulting frequencies correspond to TEST_CLK or crystal frequency of 25MHz.
Table 3C. Programmable Output Divider Function Table (PLL Enabled)
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
3
4
5
6
Output Frequency (MHz)
Minimum
206.7
155
124
103.3
Maximum
260
195
156
130
Table 3D. Commonly Used Configuration Function Table
Inputs
Crystal (MHz)
19.44
19.53125
25
25
25.50
25.50
25.50
38.88
M Divider Value
32
32
25
25
25
25
25
16
N Divider Value
4
4
4
5
3
4
6
4
Output Frequency (MHz)
Minimum
155.52
156.25
156.25
125
212.50
159.375
106.25
155.52
Table 3E. Output Enable & Clock Enable Function Table
Control Inputs
OE0
0
0
1
1
OE1
0
1
0
1
Q0
Hi-Z
Hi-Z
Enabled
Enabled
Output
Q1
Hi-Z
Enabled
Hi-Z
Enabled
84021 Rev E 9/23/15
5
©2015 Integrated Device Technology, Inc
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