74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
Rev. 11 — 31 October 2018
Product data sheet
1. General description
The 74LVT16245B; 74LVTH16245B is a high-performance BiCMOS product designed for V
CC
operation at 3.3 V.
This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both
send and receive directions. The control function implementation minimizes external timing
requirements. The device features an output enable input (nOE) for easy cascading and a direction
input (nDIR) for direction control.
2. Features and benefits
•
•
•
•
•
•
•
•
•
•
•
16-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and -32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
•
JESD78B Class II exceeds 500 mA
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVT16245BDL
74LVTH16245BDL
74LVT16245BDGG
74LVTH16245BDGG
-40 °C to +85 °C
TSSOP48
-40 °C to +85 °C
Name
SSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
Version
SOT370-1
plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
Nexperia
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
4. Functional diagram
1DIR
1OE
1A0
1B0
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2A7
2B7
001aaa789
2DIR
2OE
2A0
2B0
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
Fig. 1.
Logic symbol
74LVT_LVTH16245B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 11 — 31 October 2018
2 / 14
Nexperia
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
1OE
1DIR
48
1
G3
3EN1 [BA]
3EN2 [AB]
G6
6EN4 [BA]
6EN5 [AB]
1
2
2
3
5
6
8
9
11
12
4
5
13
14
16
17
19
20
22
23
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
25
2OE
24
2DIR
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
mna709
Fig. 2.
IEC logic symbol
74LVT_LVTH16245B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 11 — 31 October 2018
3 / 14
Nexperia
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
5. Pinning information
5.1. Pinning
74LVT16245B
74LVTH16245B
1DIR
1B0
1B1
GND
1B2
1B3
V
CC
1B4
1B5
1
2
3
4
5
6
7
8
9
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 V
CC
41 1A4
40 1A5
39 GND
38 1A6
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 V
CC
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OE
001aae471
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
V
CC
18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2DIR 24
Fig. 3.
Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
5.2. Pin description
Table 2. Pin description
Symbol
1DIR, 2DIR
1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7
2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7
GND
V
CC
1OE, 2OE
2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7
1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7
Pin
1, 24
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
48, 25
36, 35, 33, 32, 30, 29, 27, 26
47, 46, 44, 43, 41, 40, 38, 37
Description
direction control input
data input/output
data input/output
ground (0 V)
supply voltage
output enable input (active LOW)
data input/output
data input/output
74LVT_LVTH16245B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 11 — 31 October 2018
4 / 14
Nexperia
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Control
nOE
L
L
H
nDIR
L
H
X
Input/output
nAn
output nAn = nBn
input
Z
nBn
input
output nBn = nAn
Z
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
[2]
[3]
Conditions
[1]
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
Min
-0.5
-0.5
-0.5
-50
-50
-
-64
-65
[2]
-
-
Max
+4.6
+7.0
+7.0
-
-
128
-
+150
150
500
Unit
V
V
V
mA
mA
mA
mA
°C
°C
mW
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
T
amb
= -40 °C to +85 °C;
[3]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
Above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
T
amb
Δt/ΔV
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
ambient temperature
input transition rise and fall rate
none
current duty cycle ≤ 50 %; f
i
≥ 1 kHz
in free-air
outputs enabled
Min
2.7
0
2.0
-
-32
-
-
-40
-
Typ
-
-
-
-
-
-
-
-
-
Max
3.6
5.5
-
0.8
-
32
64
+85
10
Unit
V
V
V
V
mA
mA
mA
°C
ns/V
74LVT_LVTH16245B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 11 — 31 October 2018
5 / 14
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