74ALVC164245
Rev. 9 — 12 November 2018
16-bit dual supply translating transceiver; 3-state
Product data sheet
1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to
interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.
nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data
from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH, disable both
nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, nOE and nDIR are
referenced to V
CC(A)
and pins nBn are referenced to V
CC(B)
.
In suspend mode, when one of the supply voltages is zero, there will be no current flow from the
non-zero supply towards the zero supply. The nAn-outputs must be set 3-state and the voltage on
the A-bus must be smaller than V
diode
(typical 0.7 V). V
CC(B)
≥ V
CC(A)
(except in suspend mode).
2. Features and benefits
•
•
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range:
•
3 V port (V
CC(A)
): 1.5 V to 3.6 V
•
5 V port (V
CC(B)
): 1.5 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Control inputs voltage range from 2.7 V to 5.5 V
Inputs accept voltages up to 5.5 V
High-impedance outputs when V
CC(A)
or V
CC(B)
= 0 V
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
•
•
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74ALVC164245DL
74ALVC164245DGG
-40 °C to +125 °C
-40 °C to +125 °C
Name
SSOP48
TSSOP48
Description
plastic shrink small outline package;
48 leads; body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
Nexperia
74ALVC164245
16-bit dual supply translating transceiver; 3-state
4. Functional diagram
1DIR
1OE
1A0
1B0
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2A7
2B7
001aaa789
2DIR
2OE
2A0
2B0
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
Fig. 1.
Logic symbol
74ALVC164245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 9 — 12 November 2018
2 / 15
Nexperia
74ALVC164245
16-bit dual supply translating transceiver; 3-state
1OE
1DIR
2OE
2DIR
G3
3EN1[BA]
3EN2[AB]
G6
6EN4[BA]
6EN5[AB]
1A0
1
2
1B0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
4
5
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
001aaa790
Fig. 2.
IEC logic symbol
74ALVC164245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 9 — 12 November 2018
3 / 15
Nexperia
74ALVC164245
16-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1. Pinning
1DIR
1B0
1B1
GND
1B2
1B3
V
CC(B)
1B4
1B5
1
2
3
4
5
6
7
8
9
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 V
CC(A)
41 1A4
40 1A5
39 GND
38 1A6
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 V
CC(A)
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OE
001aab037
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
V
CC(B)
18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2DIR 24
74ALVC164245
Fig. 3.
Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
5.2. Pin description
Table 2. Pin description
Symbol
1DIR, 2DIR
1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7
2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7
GND
V
CC(B)
1OE, 2OE
1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7
2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7
V
CC(A)
Pin
1, 24
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39, 45
7, 18
48, 25
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
31, 42
Description
direction control input
data input/output
data input/output
ground (0 V)
supply voltage B (5 V bus)
output enable input (active LOW)
data input/output
data input/output
supply voltage A (3 V bus)
74ALVC164245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 9 — 12 November 2018
4 / 15
Nexperia
74ALVC164245
16-bit dual supply translating transceiver; 3-state
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Inputs
nOE
L
L
H
nDIR
L
H
X
Outputs
nAn
nAn = nBn
inputs
Z
nBn
inputs
nBn = nAn
Z
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(B)
V
CC(A)
I
IK
V
I
V
I/O
I
OK
V
O
Parameter
supply voltage B
supply voltage A
input clamping current
input voltage
input/output voltage
output clamping current
output voltage
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW
output 3-state
I
O(sink/source)
output sink or source current
I
CC
I
GND
T
stg
T
j
P
tot
[1]
[2]
[3]
Conditions
V
CC(B)
≥ V
CC(A)
V
CC(B)
≥ V
CC(A)
V
I
< 0 V
[1]
Min
-0.5
-0.5
-50
-0.5
-0.5
-
[1]
[1]
-0.5
-0.5
-
-
-100
-65
[2]
-
-
Max
+6.0
+4.6
-
+6.0
±50
+6.0
±50
100
-
+150
+150
500
Unit
V
V
mA
V
mA
V
mA
mA
mA
°C
°C
mW
V
CC
+ 0.5 V
V
CC
+ 0.5 V
V
O
= 0 V to V
CC
supply current
ground current
storage temperature
junction temperature
total power dissipation
T
amb
= -40 °C to +125 °C
[3]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
Above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
74ALVC164245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 9 — 12 November 2018
5 / 15
Microchip MCU
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