SiT9003
Low Power Spread Spectrum Oscillator
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
Frequency range from 1 MHz to 110 MHz
LVCMOS/LVTTL compatible output
Standby current as low as 0.4 µA
Fast resume time of 3 ms (Typ)
<30 ps cycle-to-cycle jitter
Spread options (contact SiTime for other spread options)
•
Center spread: ±0.50%, ±0.25%
•
Down spread: -1%, -0.5%
Standby, output enable, or spread disable mode
Industry-standard packages: 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2,
7.0 x 5.0 mm x mm
Outstanding mechanical robustness for portable applications
All-silicon device with outstanding reliability of 2 FIT
(10x improvement over quartz-based devices), enhancing system
mean-time-to-failure (MTBF)
Pb-free, RoHS and REACH compliant
Printers
Flat panel drivers
PCI
Microprocessors
DC Electrical Characteristics
Parameters
Output Frequency Range
Frequency Tolerance
Symbol
f
F_tol
Min.
1
-50
-100
Aging
Operating Temperature Range
Supply Voltage
Ag
T_use
Vdd
-1
-20
-40
1.71
2.25
2.52
2.97
Current Consumption
Standby Current
Idd
I_std
–
–
–
–
–
Duty Cycle
Rise/Fall Time
Output Voltage High
DC
Tr, Tf
VOH
45
40
–
-
90%
Typ.
–
–
–
–
–
–
1.8
2.5
2.8
3.3
3.7
3.2
2.4
1.2
0.4
–
–
1
1.3
–
Max.
110
+50
+100
1
+70
+85
1.89
2.75
3.08
3.63
4.1
3.5
4.3
2.2
0.8
55
60
2
2.5
–
Unit
MHz
PPM
PPM
PPM
°C
°C
V
V
V
V
mA
mA
No load condition, f = 20 MHz, Vdd = 2.5 V, 2.8 V or 3.3 V
No load condition, f = 20 MHz, Vdd = 1.8 V
ST = GND, Vdd = 3.3 V, Output is Weakly Pulled Down
ST = GND, Vdd = 2.5 or 2.8 V, Output is Weakly Pulled Down
ST = GND, Vdd = 1.8 V, Output is Weakly Pulled Down
All Vdds. f <= 70 MHz
All Vdds. f >70 MHz
20% - 80% Vdd=2.5 V, 2.8 V or 3.3 V, 15 pf load
20% - 80% Vdd=1.8 V, 15 pf load
IOH = -4 mA (Vdd = 3.3 V)
IOH = -3 mA (Vdd = 2.8 V and 2.5 V)
IOH = -2 mA (Vdd = 1.8 V)
Output Voltage Low
VOL
Output Load
Input Voltage High
Input Voltage Low
Startup Time
Resume Time
Cycle-to-Cycle Jitter
Ld
VIH
VIL
T_start
T_resume
T_cyc
–
70%
–
–
–
–
–
–
–
–
–
3.0
–
–
15
–
30%
10
3.8
26
26
pF
Vdd
Vdd
ms
ms
ps
ps
–
–
10
%Vdd
IOL = -4 mA (Vdd = 3.3 V)
IOL = -3 mA (Vdd = 2.8 V and 2.5 V)
IOL = -2 mA (Vdd = 1.8 V)
At maximum frequency and supply voltage. Contact SiTime for
higher output load option
Pin 1, OE or ST or SD
Pin 1, OE or ST or SD
Measured from the time Vdd reaches its rated minimum value
Measured from the time ST pin crosses 50% threshold
f = 50 MHz, Spread = ON
f = 50 MHz, Spread = OFF
Inclusive of: Initial stability, operating temperature, rated power,
supply voltage change, load change, shock and vibration
Spread Off
1st year at 25°C
Extended Commercial
Industrial
Condition
µ
A
µ
A
µ
A
%
%
ns
ns
Vdd
SiTime Corporation
Rev. 1.7
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised November 18, 2013
SiT9003
Low Power Spread Spectrum Oscillator
The Smart Timing Choice
The Smart Timing Choice
Spread Spectrum Modes
[1]
Center Spread
Code
Percentage
B
±0.25%
D
±0.50%
[2]
O
-0.5%
Down Spread
Q
-1.0%
[2]
Notes:
1. In both center spread and down spread modes, triangle modulation is employed with a frequency of ~32 kHz.
2. ±0.5% and -1.0% are available ONLY for <75 MHz in extended commercial temperature range.
Pin Configuration
Pin
Symbol
Standby (ST)
1
ST/OE/SD
Output Enable (OE)
Spread Disable (SD)
2
3
4
GND
CLK
VDD
Ground
Output
Power Supply
Functionality
H or Open
[3]
: specified frequency output
L: output is low (weak pull down). Oscillator stops
H or Open : specified frequency output
L: output is high impedance.
H or Open: Spread = ON
L: Spread =OFF
Connect to Ground
Clock Output
[3]
Top View
ST/OE/SD
1
4
VDD
GND
2
3
CLK
Note:
3. In 1.8 V mode, a resistor of <10 kΩ between OE pin and VDD is recommended.
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameters
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Number of Program Writes
Program Retention over -40 to 125C, Process, VDD (0 to 3.65V)
Min.
-65
-0.5
–
–
–
–
Max.
150
4
2000
260
1
1,000+
Unit
°C
V
V
°C
NA
years
Thermal Considerations
Junction-to-Ambient Thermal
Resistance (°C/W)
Package
7050
7050
7050
5032
3225
2520
Lead Count
4
4
4
4
4
4
Center Pad
Soldered down
Not soldered down
No center pad
No center pad
No center pad
No center pad
4 Layer Board
[5]
43.6
191
142
96.8
109
117
2 Layer Board
[4]
229
263
273
199
212
222
Junction-to-Case
[6]
(bottom)
Thermal Resistance
(°C/W)
2.6
2.6
29.8
24
27
26
Notes:
4. Test boards compliant with JESD51-3.
5. Test boards compliant with JESD51-7.
6. Referenced to bottom of case.
Rev. 1.7
Page 2 of 9
www.sitime.com
SiT9003
Low Power Spread Spectrum Oscillator
The Smart Timing Choice
The Smart Timing Choice
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensibility Level
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1
Condition/Test Method
Startup and Resume Timing Diagram
90% Vdd: 2.5/2.8/3.3V parts
95% Vdd: 1.8V parts
Vdd
Vdd
Pin 4 Voltage
ST Voltage
50% Vdd
T_resume
T_start
CLK Output
CLK Output
T_start: Time to start from power-off
(ST/OE Mode)
T_resume: Time to resume from ST
(ST Mode Only)
Rev. 1.7
Page 3 of 9
www.sitime.com
SiT9003
Low Power Spread Spectrum Oscillator
The Smart Timing Choice
The Smart Timing Choice
Programmable Drive Strength
The SiT9003 includes a programmable drive strength feature
to provide a simple, flexible tool to optimize the clock rise/fall
time for specific applications. Benefits from the programmable
drive strength feature are:
• Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time
• Improves the downstream clock receiver’s (RX) jitter by de-
creasing (speeding up) the clock rise/fall time.
• Ability to drive large capacitive loads while maintaining full
swing with sharp edge rates.
For more detailed information about rise/fall time control and
drive strength selection, see the SiTime Applications Note
section;
http://www.sitime.com/support/application-notes.
increases. As an example, for a 3.3V SiT9003 device with
default drive strength setting, the typical rise/fall time is 1.1ns
for 15 pF output load. The typical rise/fall time slows down to
2.9ns when the output load increases to 45 pF. One can
choose to speed up the rise/fall time to 1.9ns by then
increasing the drive strength setting on the SiT9003.
The SiT9003 can support up to 60 pF or higher in maximum
capacitive loads with up to 3 additional drive strength settings.
Refer to the
Rise/Tall Time Tables
to determine the proper
drive strength for the desired combination of output load vs.
rise/fall time
SiT9003 Drive Strength Selection
Tables 1 through 4 define the rise/fall time for a given capac-
itive load and supply voltage.
1. Select the table that matches the SiT9003 nominal supply
voltage (1.8V, 2.5V, 2.8V, 3.3V).
2. Select the capacitive load column that matches the appli-
cation requirement (15 pF to 60 pF)
3. Under the capacitive load column, select the desired
rise/fall times.
4. The left-most column represents the part number code for
the corresponding drive strength.
5. Add the drive strength code to the part number for ordering
purposes.
EMI Reduction by Slowing Rise/Fall Time
Figure 1 shows the harmonic power reduction as the rise/fall
times are increased (slowed down). The rise/fall times are
expressed as a ratio of the clock period. For the ratio of 0.05,
the signal is very close to a square wave. For the ratio of 0.45,
the rise/fall times are very close to near-triangular waveform.
These results, for example, show that the 11th clock harmonic
can be reduced by 35 dB if the rise/fall edge is increased from
5% of the period to 45% of the period.
10
0
trise=0.05
trise=0.1
trise=0.15
trise=0.2
trise=0.25
trise=0.3
trise=0.35
trise=0.4
trise=0.45
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables 1 through
4, the maximum frequency the oscillator can operate with
guaranteed full swing of the output voltage over temperature
as follows:
M a x F re q u e n c y =
1
5 x T rf_ 2 0 /8 0
Harmonic amplitude (dB)
-10
-20
-30
-40
-50
-60
-70
-80
1
3
5
7
9
11
Harm onic num ber
Where Trf_20/80 is the typical rise/fall time at 20% to 80%
Vdd
Example 1
Calculate f
MAX
for the following condition:
• Vdd = 3.3V (Table 1)
• Capacitive Load: 30 pF
• Desired Tr/f time = 1.6ns (rise/fall time part number code =
Z)
Part number for the above example:
SiT9003AIZ14-33EB-105.12345
Figure 1. Harmonic EMI reduction as a Function of
Slower Rise/Fall Time
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the
downstream chipset. One way to reduce this jitter is to
increase rise/fall time (edge rate) of the input clock. Some
chipsets would require faster rise/fall time in order to reduce
their sensitivity to this type of jitter. The SiT9003 provides up
to 3 additional high drive strength settings for very fast rise/fall
time. Refer to the
Rise/Fall Time Tables
to determine the
proper drive strength.
High Output Load Capability
The rise/fall time of the input clock varies as a function of the
actual capacitive load the clock drives. At any given drive
strength, the rise/fall time becomes slower as the output load
Drive strength code is inserted here. Default setting is “-”
Rev. 1.7
Page 4 of 9
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SiT9003
Low Power Spread Spectrum Oscillator
The Smart Timing Choice
The Smart Timing Choice
Rise and Fall Time Tables
Table 1. Rise/Fall Times, VDD = 3.3V
±10%,
T = 40°C to 85°C
Load (pF)
Drive Strength
U
x or “–”: Default
Z
H
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
15
2.4
1.7
2.0
1.1
1.2
0.8
0.9
0.6
30
3.5
2.8
2.5
2.0
2.0
1.6
1.7
1.3
45
5.5
4.3
3.9
2.9
3.0
2.2
2.5
1.9
60
6.4
5.4
4.8
3.8
3.7
2.9
3.0
2.3
Drive Strength
U
X
x or “–”: Default
H
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
15
2.8
2.1
2.3
1.4
2.0
1.1
1.3
0.9
Table 3. Rise/Fall Times, VDD = 2.5V
±10%,
T = 40°C to 85°C
Load (pF)
30
4.6
3.6
3.3
2.5
2.6
1.9
2.2
1.6
45
6.8
5.2
5.0
3.7
3.4
2.8
3.3
2.3
60
8.3
6.4
5.9
4.7
4.8
3.6
4.0
2.9
Table 2. Rise/Fall Times, VDD = 2.8V
±10%,
T = 40°C to 85°C
Load (pF)
Drive Strength
U
X
x or “–”: Default
H
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
15
2.5
2.0
2.2
1.3
2.0
1.0
1.2
0.7
30
4.1
3.2
3.0
2.2
2.4
1.7
1.9
1.5
45
6.0
4.8
4.5
3.3
3.5
2.5
2.9
2.0
60
7.3
5.9
5.4
4.3
4.3
3.2
3.6
2.6
Table 4. Rise/Fall Times, VDD = 1.8V
±5%,
T = 40°C to 85°C
Load (pF)
Drive Strength
U
X
Z
x or “–”: Default
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
15
4.2
3.1
3.2
2.3
2.7
1.7
2.5
1.4
30
6.8
5.1
4.9
3.7
3.9
2.9
3.3
2.4
45
9.4
7.3
6.9
5.3
5.5
4.2
4.6
3.4
60
12.1
9.2
8.7
6.5
6.7
5.2
5.7
4.3
Note:
7. All rise/fall times are measured for the thresholds of 20% to 80% of VDD.
Rev. 1.7
Page 5 of 9
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