All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
Document #: 38-05513 Rev. *A
Page 4 of 14
PRELIMINARY
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Because the CY7C1351G is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQs and DQP
[A:D]
inputs. Doing
so will tri-state the output drivers. As a safety precaution, DQs
and DQP
[A:D]
.are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1351G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE
1
, CE
2
, and CE
3
) and WE inputs are
ignored and the burst counter is incremented. The correct
BW
[A:D]
inputs must be driven in each cycle of the burst write,
in order to write the correct bytes of data.
Sleep Mode
CY7C1351G
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3
, must remain inactive for
the duration of t
ZZREC
after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Interleaved Burst Address Table (MODE =
Floating or V
DD
)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
00
11
10
Third
Address
A1, A0
10
11
00
01
Min.
Max.
40
2t
CYC
2t
CYC
0
Fourth
Address
A1, A0
11
10
01
00
Unit
mA
ns
ns
ns
ns
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ inactive to exit snooze current
Test Conditions
ZZ > V
DD
−
0.2V
ZZ > V
DD
−
0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
2t
CYC
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin Burst)
DUMMY READ (Continue Burst)
Address
Used
CE
1
CE
2
CE
3
ZZ ADV/LD WE BW
X
OE CEN CLK
DQ
None
H
X
X
L
L
X
X
X
L
L->H
tri-state
None
X
X
H
L
L
X
X
X
L
L->H
tri-state
None
X
L
X
L
L
X
X
X
L
L->H
tri-state
None
X
X
X
L
H
X
X
X
L
L->H
tri-state
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
tri-state
Next
X
X
X
L
H
X
X
H
L
L->H
tri-state
Notes:
2. X = Don’t Care.” H= Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BW
X
, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP
[A:D]
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
[A:D]
= tri-state when
OE is inactive or when the device is deselected, and DQs and DQP
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