Data Sheet No. PD94124
IRU1030
3A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
DESCRIPTION
The IRU1030 is a low dropout three-terminal adjustable
regulator with minimum of 3A output current capability.
This product is specifically designed to provide well regu-
lated supply for low voltage IC applications such as
Pentium™ P54C™ , P55C™ as well as GTL+ termina-
tion for Pentium Pro™ and Klamath™ processor appli-
cations. The IRU1030 is also well suited for other pro-
cessors such as Cyrix™ , AMD and Power PC™ appli-
cations. The IRU1030 is guaranteed to have <1.3V drop-
out at full load current making it ideal to provide well
regulated outputs of 2.5V to 3.3V with 4.75V to 7V input
supply.
FEATURES
Guaranteed < 1.3V Dropout at Full Load Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-In Thermal Shutdown
APPLICATIONS
Low Voltage Processor Applications such as:
P54C™ , P55C™ , Cyrix M2™ ,
POWER PC™ , AMD
GTL+ Termination
PENTIUM PRO™ , KLAMATH™
Low Voltage Memory Termination Applications
Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
5V
C1
1500uF
V
IN
3
IRU1030
V
OUT
2
R1
121
3.3V / 3A
C2
1500uF
Adj
1
R2
200
Figure 1 - Typical Application of IRU1030 in a 5V to 3.3V regulator.
Notes:
Pentium P54C, P55C, Klamath, Pentium Pro, VRE are trademarks of Intel Corp.Cyrix M2 is trademark of Cyrix Corp.
Power PC is trademark of IBM Corp.
PACKAGE ORDER INFORMATION
T
J
(°C)
0 To 150
2-PIN PLASTIC
TO-252 (D-Pak)
IRU1030CD
3-PIN PLASTIC
TO-263 (M)
IRU1030CM
3-PIN PLASTIC
TO-220 (T)
IRU1030CT
Rev. 1.3
08/20/02
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1
IRU1030
ABSOLUTE MAXIMUM RATINGS
Input Voltage (V
IN
) ....................................................
Power Dissipation .....................................................
Storage Temperature Range ......................................
Operating Junction Temperature Range .....................
7V
Internally Limited
-65°C To 150°C
0°C To 150°C
PACKAGE INFORMATION
2-PIN PLASTIC TO-252 (D-Pak)
FRONT VIEW
3
3-PIN PLASTIC TO-263 (M)
FRONT VIEW
3
3-PIN PLASTIC TO-220 (T)
FRONT VIEW
V
IN
Tab is
V
OUT
V
IN
V
OUT
Adj
Tab is
V
OUT
3
V
IN
V
OUT
Adj
Tab is
V
OUT
1
2
2
Adj
1
1
θ
JA
=70°C/W for 0.5" Square pad
θ
JA
=35°C/W for 1" Square pad
θ
JT
=2.7°C/W
θ
JA
=60°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over C
IN
=1mF, C
OUT
=10mF, and T
J
=0 to 1508C.
Typical values refer to T
J
=258C.
PARAMETER
Reference Voltage
Line Regulation
Load Regulation (Note 1)
Dropout Voltage (Note 2)
Current Limit
Minimum Load Current (Note 3)
Thermal Regulation
Ripple Rejection
Adjust Pin Current
Adjust Pin Current Change
Temperature Stability
Long Term Stability
RMS Output Noise
SYM
V
REF
TEST CONDITION
Io=10mA, T
J
=258C, (V
IN
-Vo)=1.5V
Io=10mA, (V
IN
-Vo)=1.5V
Io=10mA, 1.3V<(V
IN
-Vo)<7V
V
IN
=3.3V, V
ADJ
=0, 10mA<Io<3A
Note 2, Io=3A
V
IN
=3.3V,
DVo=100mV
V
IN
=3.3V, V
ADJ
=0V
30ms Pulse, V
IN
-Vo=3V, Io=3A
f=120Hz, Co=25mF Tantalum,
Io=1.5A, V
IN
-Vo=3V
Io=10mA, V
IN
-Vo=1.5V, T
J
=258C,
Io=10mA, V
IN
-Vo=1.5V
Io=10mA, V
IN
-Vo=1.5V, T
J
=258C
V
IN
=3.3V, V
ADJ
=0V, Io=10mA
T
J
=1258C, 1000Hrs
T
J
=258C, 10Hz<f<10KHz
MIN
1.238
1.225
TYP
1.250
1.250
MAX
1.262
1.275
0.2
0.4
1.3
10
0.02
UNITS
V
%
%
V
A
mA
%/W
dB
120
5
1
mA
mA
%
%
%V
O
DV
O
1.1
3.1
5
0.01
60
70
55
0.2
0.5
0.3
0.003
I
ADJ
Note 1:
Low duty cycle pulse testing with Kelvin con-
nections is required in order to maintain accurate data.
Note 2:
Dropout voltage is defined as the minimum dif-
ferential voltage between V
IN
and V
OUT
required to main-
tain regulation at V
OUT
. It is measured when the output
voltage drops 1% below its nominal value.
Note 3:
Minimum load current is defined as the mini-
mum current required at the output in order for the out-
put voltage to maintain regulation. Typically the resistor
dividers are selected such that this current is automati-
cally maintained.
2
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Rev. 1.3
08/20/02
IRU1030
PIN DESCRIPTIONS
PIN #
1
2
PIN SYMBOL
Adj
V
OUT
PIN DESCRIPTION
A resistor divider from V
OUT
to Adj pin to ground sets the output voltage.
The output of the regulator. A minimum of 10µF capacitor must be connected from this pin
to ground to insure stability.
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum drop out
voltage during the load transient response. This pin must always be 1.3V higher than V
OUT
in order for the device to regulate properly.
3
V
IN
BLOCK DIAGRAM
V
IN
3
2 V
OUT
+
+
1.25V
CURRENT
LIMIT
THERMAL
SHUTDOWN
Figure 2 - Simplified block diagram of the IRU1030.
1 Adj
APPLICATION INFORMATION
Introduction
The IRU1030 adjustable Low Dropout (LDO) regulator is
a three-terminal device which can easily be programmed
with the addition of two external resistors to any volt-
ages within the range of 1.25 to 5.5V. This regulator un-
like the first generation of the three-terminal regulators
such as LM117 that required 3V differential between the
input and the regulated output, only needs 1.3V differen-
tial to maintain output regulation. This is a key require-
ment for today’s microprocessors that need typically
3.3V supply and are often generated from the 5V sup-
ply. Another major requirement of these microproces-
sors such as the Intel P54C™ is the need to switch the
load current from zero to several amps in tens of nano-
Rev. 1.3
08/20/02
seconds at the processor pins, which translates to an
approximately 300 to 500ns current step at the regula-
tor. In addition, the output voltage tolerances are also
extremely tight and they include the transient response
as part of the specification. For example Intel VRE™
specification calls for a total of
±100mV
including initial
tolerance, load regulation and 0 to 4.6A load step.
The IRU1030 is specifically designed to meet the fast
current transient needs as well as providing an accurate
initial voltage, reducing the overall system cost with the
need for fewer output capacitors.
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3
IRU1030
Output Voltage Setting
The IRU1030 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
V
OUT
= V
REF
3
1+
to the load side, the effective resistance between the
regulator and the load is gained up by the factor of (1+R2/
R1), or the effective resistance will be R
P(eff)
=R
P
3(1+R2/
R1). It is important to note that for high current applica-
tions, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to mini-
mize this effect.
PARASITIC LINE
RESISTANCE
(
R2
R1
)
+I
ADJ
3R2
Where:
V
REF
= 1.25V Typically
I
ADJ
= 50mA Typically
R1 and R2 as shown in Figure 3:
V
IN
V
IN
V
OUT
R
P
IRU1030
V
IN
V
IN
V
OUT
V
OUT
Adj
IRU1030
Adj
R1
R
L
R2
V
REF
R1
I
ADJ
= 50uA
R2
Figure 4 - Schematic showing connection
for best load regulation.
Figure 3 - Typical application of the IRU1030
for programming the output voltage.
The IRU1030 keeps a constant 1.25V between the out-
put pin and the adjust pin. By placing a resistor R1 across
these two pins a constant current flows through R1, add-
ing to the I
ADJ
current and into the R2 resistor producing
a voltage equal to the (1.25/R1)3R2 + I
ADJ
3R2
which
will be added to the 1.25V to set the output voltage.
This is summarized in the above equation. Since the
minimum load current requirement of the IRU1030 is
10mA, R1 is typically selected to be 121V resistor so
that it automatically satisfies the minimum current re-
quirement. Notice that since I
ADJ
is typically in the range
of 50mA it only adds a small error to the output voltage
and should only be considered when a very precise out-
put voltage setting is required. For example, in a typical
3.3V application where R1=121V and R2=200V the er-
ror due to I
ADJ
is only 0.3% of the nominal set point.
Load Regulation
Since the IRU1030 is only a three-terminal device, it is
not possible to provide true remote sensing of the output
voltage at the load. Figure 4 shows that the best load
regulation is achieved when the bottom side of R2 is
connected to the load and the top side of R1 resistor is
connected directly to the case or the V
OUT
pin of the
regulator and not to the load. In fact, if R1 is connected
Stability
The IRU1030 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for microprocessor ap-
plications use standard electrolytic capacitors with a
typical ESR in the range of 50 to 100mV and an output
capacitance of 500 to 1000mF. Fortunately as the ca-
pacitance increases, the ESR decreases resulting in a
fixed RC time constant. The IRU1030 takes advantage
of this phenomena in making the overall regulator loop
stable. For most applications a minimum of 100mF alu-
minum electrolytic capacitor such as Sanyo MVGX se-
ries, Panasonic FA series as well as the Nichicon PL
series insures both stability and good transient response.
Thermal Design
The IRU1030 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
tures in the range of 1508C, it is recommended that the
selected heat sink be chosen such that during maxi-
mum continuous load operation the junction tempera-
ture is kept below this number. The example below
shows the steps in selecting the proper regulator heat
sink for the GTL+ terminator using a separate regulator
for each end.
4
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Rev. 1.3
08/20/02
IRU1030
Assuming the following specifications:
V
IN
= 3.3V
V
OUT
= 1.5V
I
OUT(MAX)
= 2.7A
T
A
= 358C
The steps for selecting a proper heat sink to keep the
junction temperature below 135°C is given as:
1) Calculate the maximum power dissipation using:
P
D
= I
OUT
3(V
IN
- V
OUT
)
P
D
= 2.73(3.3 - 1.5) = 4.86W
2) Select a package from the regulator data sheet and
record its junction to case (or tab) thermal resistance.
Selecting TO-220 package gives us:
u
JC
= 2.78C/W
3) Assuming that the heat sink is black anodized, cal-
culate the maximum heat sink temperature allowed:
Assume,
ucs=0.05°C/W
(heat-sink-to-case thermal
resistance for black anodized)
T
S
= T
J
- P
D
3(u
JC
+
u
CS
)
T
S
= 135 - 4.863(2.7 + 0.05) = 121.78C
4) With the maximum heat sink temperature calculated
in the previous step, the heat-sink-to-air thermal re-
sistance (u
SA
) is calculated by first calculating the
temperature rise above the ambient as follows:
DT
= T
S
- T
A
= 121.7 - 35 = 86.78C
∆T=Temperature
Rise Above Ambient
u
SA
=
DT
86.7
=
= 17.88C/W
P
D
4.86
Air Flow (LFM)
0
100
200
300
Thermalloy 6109PB 6110PB
7141
7178
AAVID
575002 507302 576802B 577102
Note:
For further information regarding the above com-
panies and their latest product offerings and application
support contact your local representative or the num-
bers listed below:
AAVID................PH# (603) 528 3400
Thermalloy..........PH# (214) 243-4321
Designing for Microprocessor Applications
As it was mentioned before the IRU1030 is designed
specifically to provide power for the new generation of
the low voltage processors requiring voltages in the range
of 2.5V to 3.6V generated by stepping down the 5V
supply. These processors demand a fast regulator that
supports their large load current changes. The worst case
current step seen by the regulator is anywhere in the
range of 1 to 7A with the slew rate of 300 to 500ns which
could happen when the processor transitions from “Stop
Clock” mode to the “Full Active” mode. The load current
step at the processor is actually much faster, in the or-
der of 15 to 20ns, however the decoupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
levels. Because of this requirement the selection of high
frequency low ESR and low ESL output capacitors is
imperative in the design of these regulator circuits.
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neous drop equal to the (∆V
ESR
=ESR3∆I) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (
ESL
∆V
=L3∆I/∆t). The output capacitance effect is a droop in
the output voltage proportional to the time it takes for the
regulator to respond to the change in the current,
(∆Vc=∆t3∆I/C) where
∆t
is the response time of the
regulator.
5) Next, a heat sink with lower
u
SA
than the one calcu-
lated in step 4 must be selected. One way to do this
is to simply look at the graphs of the “Heat Sink Temp
Rise Above the Ambient” vs. the “Power Dissipation”
and select a heat sink that results in lower tempera-
ture rise than the one calculated in the previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
Rev. 1.3
08/20/02
www.irf.com
5
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