PD- 91317C
IRLR/U2705
HEXFET
®
Power MOSFET
l
l
l
l
l
l
l
Logic-Level Gate Drive
Ultra Low On-Resistance
Surface Mount (IRLR2705)
Straight Lead (IRLU2705)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
D
V
DSS
= 55V
G
S
R
DS(on)
= 0.040Ω
I
D
= 28A
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per
silicon area. This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs are well known for,
provides the designer with an extremely efficient device for use in a wide
variety of applications.
The D-PAK is designed for surface mounting using vapor phase, infrared, or
wave soldering techniques. The straight lead version (IRFU series) is for
through-hole mounting applications. Power dissipation levels up to 1.5 watts
are possible in typical surface mount applications.
D-Pak
TO-252AA
I-Pak
TO-251AA
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
28
20
110
68
0.45
± 16
110
16
6.8
5.0
-55 to + 175
300 (1.6mm from case )
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
R
θJA
Junction-to-Case
Case-to-Ambient (PCB mount)**
Junction-to-Ambient
Typ.
–––
–––
–––
Max.
2.2
50
110
Units
°C/W
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
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1
4/1/03
IRLR/U2705
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
Min. Typ. Max. Units
Conditions
55
––– –––
V
V
GS
= 0V, I
D
= 250µA
––– 0.065 ––– V/°C Reference to 25°C, I
D
= 1mA
–––
––– 0.040
V
GS
= 10V, I
D
= 17A
–––
––– 0.051
W
V
GS
= 5.0V, I
D
= 17A
–––
––– 0.065
V
GS
= 4.0V, I
D
= 14A
1.0
––– 2.0
V
V
DS
= V
GS
, I
D
= 250µA
11
––– –––
S
V
DS
= 25V, I
D
= 16A
––– ––– 25
V
DS
= 55V, V
GS
= 0V
µA
–––
––– 250
V
DS
= 44V, V
GS
= 0V, T
J
= 150°C
––– ––– 100
V
GS
= 16V
nA
––– ––– -100
V
GS
= -16V
––– ––– 25
I
D
= 16A
–––
––– 5.2
nC V
DS
= 44V
––– ––– 14
V
GS
= 5.0V, See Fig. 6 and 13
–––
8.9 –––
V
DD
= 28V
––– 100 –––
I
D
= 16A
ns
–––
21 –––
R
G
= 6.5Ω, V
GS
= 5.0V
–––
29 –––
R
D
= 1.8Ω, See Fig. 10
Between lead,
4.5
nH
6mm (0.25in.)
G
from package
––– 7.5 –––
and center of die contact
––– 880 –––
V
GS
= 0V
––– 220 –––
pF
V
DS
= 25V
–––
94 –––
ƒ = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 28
showing the
A
G
integral reverse
––– ––– 110
S
p-n junction diode.
––– ––– 1.3
V
T
J
= 25°C, I
S
= 17A, V
GS
= 0V
––– 76 110
ns
T
J
= 25°C, I
F
= 16A
––– 190 290
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
V
DD
= 25V, starting T
J
= 25°C, L = 610µH
R
G
= 25Ω, I
AS
= 16A. (See Figure 12)
I
SD
≤
16A, di/dt
≤
270A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C
Pulse width
≤
300µs; duty cycle
≤
2%.
Caculated continuous current based on maximum allowable
junction temperature; Package limitation current = 20A.
This is applied for I-PAK, L
S
of D-PAK is measured between
lead and center of die contact.
Uses IRLZ34N data and test conditions.
2
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IRLR/U2705
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
1000
I
D
, Drain-to-Source Current (A)
100
I
D
, Drain-to-Source Current (A)
100
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
10
10
2.5V
1
1
2.5V
0.1
0.1
20µs PULSE WIDTH
T
J
= 25°C
1
10
100
A
0.1
0.1
20µs PULSE WIDTH
T
J
= 175°C
1
10
100
A
V
DS
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
3.0
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
I
D
= 27A
I
D
, Drain-to-Source Current (A)
2.5
100
T
J
= 25°C
T
J
= 175°C
2.0
10
1.5
1.0
1
0.5
0.1
2
3
4
5
6
V
DS
= 25V
20µs PULSE WIDTH
7
8
9
10
A
0.0
-60 -40 -20
0
20
40
60
V
GS
= 10V
80 100 120 140 160 180
A
V
GS
, Gate-to-Source Voltage (V)
T
J
, Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
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3
IRLR/U2705
1400
V
GS
, Gate-to-Source Voltage (V)
1200
V
GS
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd
, C
ds
SHORTED
C
rss
= C
gd
C
iss
C
oss
= C
ds
+ C
gd
15
I
D
= 16A
V
DS
= 44V
V
DS
= 28V
12
C, Capacitance (pF)
1000
800
9
C
oss
600
6
400
C
rss
200
3
0
1
10
100
A
0
0
4
8
12
16
FOR TEST CIRCUIT
SEE FIGURE 13
20
24
28
32
A
V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
I
D
, Drain Current (A)
100
100
10µs
T
J
= 175°C
T
J
= 25°C
10
100µs
10
1ms
1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
GS
= 0V
1.8
A
1
1
T
C
= 25°C
T
J
= 175°C
Single Pulse
10
10ms
A
100
2.0
V
SD
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
4
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IRLR/U2705
30
LIMITED BY PACKAGE
25
V
DS
V
GS
R
G
R
D
D.U.T.
+
I
D
, Drain Current (A)
20
-
V
DD
5V
15
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
10
Fig 10a.
Switching Time Test Circuit
V
DS
90%
5
0
25
50
75
100
125
150
175
T
C
, Case Temperature ( °C)
10%
V
GS
Fig 9.
Maximum Drain Current Vs.
Case Temperature
t
d(on)
t
r
t
d(off)
t
f
Fig 10b.
Switching Time Waveforms
10
Thermal Response (Z
thJC
)
1
D = 0.50
0.20
0.10
0.05
P
DM
SINGLE PULSE
(THERMAL RESPONSE)
t
1
t
2
Notes:
1. Duty factor D = t
1
/ t
2
2. Peak T
J
= P
DM
x Z
thJC
+ T
C
0.0001
0.001
0.01
0.1
0.1
0.02
0.01
0.01
0.00001
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
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