PD - 9.1692A
PRELIMINARY
l
l
l
l
l
IRL3302S
HEXFET
®
Power MOSFET
D
Advanced Process Technology
Surface Mount
Optimized for 4.5V-7.0V Gate Drive
Ideal for CPU Core DC-DC Converters
Fast Switching
V
DSS
= 20V
G
S
R
DS(on)
= 0.020W
I
D
= 39A
Description
These HEXFET Power MOSFETs were designed
specifically to meet the demands of CPU core DC-DC
converters. Advanced processing techniques
combined with an optimized gate oxide design results
in a die sized specifically to offer maximum efficiency
at minimum cost.
The D
2
Pak is a surface mount power package capable
of accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because
of its low internal connection resistance and can
dissipate up to 2.0W in a typical surface mount
application.
D
2
P ak
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 4.5V
Continuous Drain Current, V
GS
@ 4.5V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
39
25
160
57
0.45
± 10
130
23
5.7
5.0
-55 to + 150
300 (1.6mm from case )
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
qJC
R
qJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
–––
–––
Max.
2.2
40
Units
°C/W
9/17/97
IRL3302S
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
V
(BR)DSS
Drain-to-Source Breakdown Voltage
DV
(BR)DSS
/DT
J
Breakdown Voltage Temp. Coefficient
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min.
20
–––
–––
–––
0.70
21
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.022
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
7.2
110
41
89
Max. Units
Conditions
–––
V
V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 1mA
0.023
V
GS
= 4.5V, I
D
= 23A
W
0.020
V
GS
= 7.0V, I
D
= 23A
–––
V
V
DS
= V
GS
, I
D
= 250µA
–––
S
V
DS
= 10V, I
D
= 23A
25
V
DS
= 20V, V
GS
= 0V
µA
250
V
DS
= 10V, V
GS
= 0V, T
J
= 150°C
100
V
GS
= 10V
nA
-100
V
GS
= -10V
31
I
D
= 23A
5.7
nC
V
DS
= 16V
13
V
GS
= 4.5V, See Fig. 6
–––
V
DD
= 10V
–––
I
D
= 23A
ns
–––
R
G
= 9.5W V
GS
= 4.5V
,
–––
R
D
= 2.4W
,
Between lead,
nH
7.5 –––
and center of die contact
1300 –––
V
GS
= 0V
520 –––
pF
V
DS
= 15V
190 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery
Forward Turn-On Time
Conditions
D
MOSFET symbol
39
––– –––
showing the
A
G
integral reverse
––– ––– 160
S
p-n junction diode.
––– ––– 1.3
V
T
J
= 25°C, I
S
= 23A, V
GS
= 0V
––– 62
94
ns
T
J
= 25°C, I
F
= 23A
Charge ––– 110
160 nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Min. Typ. Max. Units
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
I £
23A, di/dt
£
97A/µs, V
DD
£
V
(BR)DSS
,
SD
T
J
£
150°C
Starting T
J
= 25°C, L = 0.49mH
R
G
= 25W , I
AS
= 23A.
Pulse width
£
300µs; duty cycle
£
2%.
Uses IRL3302 data and test conditions
** When mounted on FR-4 board using minimum recommended footprint.
For recommended footprint and soldering techniques refer to application note #AN-994.
IRL3302S
1000
VGS
VGS
15V
10V
12V
8.0V
10V
6.0V
8.0V
4.0V
6.0V
4.0V
3.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
TOP
TOP
1000
I
D
, Drain-to-Source Current (A)
100
I
D
, Drain-to-Source Current (A)
VGS
VGS
15V
10V
12V
8.0V
10V
6.0V
8.0V
4.0V
6.0V
4.0V
3.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
TOP
TOP
100
2.5V
10
0.1
2.5V
20µs PULSE WIDTH
T
J
= 25
°
C
10
0.1
20µs PULSE WIDTH
T
J
= 150
°
C
1
10
100
1
10
100
V
DS
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
2.0
T
J
= 25
°
C
T
J
= 150
°
C
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
I
D
= 39A
I
D
, Drain-to-Source Current (A)
1.5
100
1.0
10
0.5
1
2
3
4
5
V DS = 15V
20µs PULSE WIDTH
6
7
8
0.0
-60 -40 -20
V
GS
= 4.5V
0
20
40
60
80 100 120 140 160
V
GS
, Gate-to-Source Voltage (V)
T
J
, Junction Temperature(
°
C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
IRL3302S
2400
2000
V
GS
, Gate-to-Source Voltage (V)
V
GS
=
C
iss
=
C
rss
=
C
oss
=
0V,
f = 1MHz
C
gs
+ C
gd ,
C
ds
SHORTED
C
gd
C
ds
+ C
gd
15
I
D
=
23A
V
DS
= 16V
12
C, Capacitance (pF)
1600
C
iss
1200
9
6
800
C
oss
400
3
C
rss
0
1
10
100
0
0
10
20
30
40
50
V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
100
T
J
= 150
°
C
I
D
, Drain Current (A)
10us
100
100us
10
10
1ms
T
J
= 25
°
C
T
C
= 25 ° C
T
J
= 150 ° C
Single Pulse
1
10
10ms
1
0.5
V
GS
= 0 V
1.0
1.5
2.0
1
100
V
SD
,Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
IRL3302S
40
300
E
AS
, Single Pulse Avalanche Energy (mJ)
TOP
250
I
D
, Drain Current (A)
30
BOTTOM
ID
10A
15A
23A
200
20
150
100
10
50
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
C
, Case Temperature ( ° C)
Starting T
J
, Junction Temperature(
°
C)
Fig 9.
Maximum Drain Current Vs.
Case Temperature
Fig 10.
Maximum Avalanche Energy
Vs. Drain Current
10
Thermal Response (Z
thJC
)
1
D = 0.50
0.20
0.10
0.05
P
DM
SINGLE PULSE
(THERMAL RESPONSE)
t
1
t
2
Notes:
1. Duty factor D = t
1
/ t
2
2. Peak T
J
= P
DM
x Z
thJC
+ T
C
0.0001
0.001
0.01
0.1
1
0.1
0.02
0.01
0.01
0.00001
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
