PD - 91502C
IRL3705NS/L
Logic-Level Gate Drive
l
Advanced Process Technology
l
Surface Mount (IRL3705NS)
l
Low-profile through-hole (IRL3705NL)
l
175°C Operating Temperature
l
Fast Switching
l
Fully Avalanche Rated
Description
l
HEXFET
®
Power MOSFET
D
V
DSS
= 55V
R
DS(on)
= 0.01Ω
G
I
D
= 89A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL3705NL) is available for low-
profile applications.
D 2 P ak
T O -26 2
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
A
= 25°C
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
89
63
310
3.8
170
1.1
± 16
340
46
1.7
5.0
-55 to + 175
300 (1.6mm from case )
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
–––
–––
Max.
0.90
40
Units
°C/W
5/12/98
IRL3705NS/L
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
V
(BR)DSS
Drain-to-Source Breakdown Voltage
∆V
(BR)DSS
/∆T
J
Breakdown Voltage Temp. Coefficient
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min.
55
–––
–––
–––
–––
1.0
50
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.056
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
12
140
37
78
Max. Units
Conditions
–––
V
V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 1mA
0.010
V
GS
= 10V, I
D
= 46A
0.012
Ω
V
GS
= 5.0V, I
D
= 46A
0.018
V
GS
= 4.0V, I
D
= 39A
2.0
V
V
DS
= V
GS
, I
D
= 250µA
–––
S
V
DS
= 25V, I
D
= 46A
25
V
DS
= 55V, V
GS
= 0V
µA
250
V
DS
= 44V, V
GS
= 0V, T
J
= 150°C
100
V
GS
= 16V
nA
-100
V
GS
= -16V
98
I
D
= 46A
19
nC V
DS
= 44V
49
V
GS
= 5.0V, See Fig. 6 and 13
–––
V
DD
= 28V
–––
I
D
= 46A
ns
–––
R
G
= 1.8Ω, V
GS
= 5.0V
–––
R
D
= 0.59Ω, See Fig. 10
Between lead,
7.5 –––
nH
and center of die contact
3600 –––
V
GS
= 0V
870 –––
pF
V
DS
= 25V
320 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 89
showing the
A
G
integral reverse
––– ––– 310
S
p-n junction diode.
––– ––– 1.3
V
T
J
= 25°C, I
S
= 46A, V
GS
= 0V
––– 94 140
ns
T
J
= 25°C, I
F
= 46A
––– 290 440
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width
≤
300µs; duty cycle
≤
2%.
Uses IRL3705N data and test conditions
Calculated continuous current based on maximum allowable
V
DD
= 25V, starting T
J
= 25°C, L = 320µH
R
G
= 25Ω, I
AS
= 46A. (See Figure 12)
I
SD
≤
46A, di/dt
≤
250A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C
junction temperature; for recommended current-handling of the
package refer to Design Tip # 93-4
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
IRL3705NS/L
1000
TOP
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
1000
I
D
, D rain-to-S ource C urrent (A )
I
D
, Drain-to-Source Current (A )
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
100
100
10
10
2 .5V
2.5V
2 0µ s P U LS E W ID T H
T
J
= 2 5°C
0.1
1
10
1
A
1
0.1
1
2 0µ s P U LS E W ID TH
T
J
= 1 75 °C
10
100
100
A
V
D S
, D rain-to-S ource V oltage (V )
V
D S
, D rain-to-S ource V oltage (V )
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
3.0
R
D S (on )
, D rain-to-S ource O n R esistance
(N orm alized)
I
D
= 7 7A
I
D
, D ra in -to-S ourc e C urrent (A)
T
J
= 2 5 °C
100
2.5
T
J
= 1 7 5 °C
2.0
1.5
10
1.0
0.5
1
2.0
3.0
4.0
5.0
V
D S
= 2 5 V
2 0 µ s P U L S E W ID T H
6.0
7.0
8.0
A
0.0
-60
-40
-20
0
20
40
60
80
V
G S
= 10 V
100 120 140 160 180
A
V
G S
, G a te -to -S o u rc e V o lta g e (V )
T
J
, Junction T em perature (°C )
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
IRL3705NS/L
6000
5000
4000
V
G S
, G ate-to-S ource V oltage (V )
V
GS
C
iss
C
rs s
C
iss C
o ss
=
=
=
=
0V ,
f = 1MHz
C
g s
+ C
g d
, C
d s
S H O R TE D
C
gd
C
ds
+ C
g d
15
I
D
= 46 A
V
D S
= 44 V
V
D S
= 28 V
12
C , Capacitance (pF)
9
3000
C
oss
6
2000
C
rss
1000
3
0
1
10
100
A
0
0
20
40
60
FO R TE S T C IR C U IT
S E E FIG U R E 1 3
80
100
120
140
A
V
D S
, D rain-to-S ourc e V oltage (V )
Q
G
, T otal G ate C harge (nC )
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
I
SD
, Reverse D rain C urrent (A)
O P E R A T IO N IN T H IS A R E A L IM ITE D
B Y R
D S (o n)
10µ s
100
100µ s
100
T
J
= 17 5°C
T
J
= 2 5°C
I
D
, D rain Current (A )
1m s
10
10m s
10
0.4
0.8
1.2
1.6
2.0
V
G S
= 0V
2.4
A
1
1
T
C
= 25 °C
T
J
= 17 5°C
S ing le P u lse
10
100
A
2.8
V
S D
, S ourc e-to-D rain V oltage (V )
V
D S
, D rain-to-S ource V oltage (V )
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
IRL3705NS/L
100
LIMITED BY PACKAGE
80
V
DS
V
GS
R
G
R
D
D.U.T.
V
DD
-
+
I
D
, Drain Current (A)
60
5.0V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
40
Fig 10a.
Switching Time Test Circuit
20
V
DS
90%
0
25
50
75
100
125
150
175
T
C
, Case Temperature ( ° C)
Fig 9.
Maximum Drain Current Vs.
Case Temperature
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b.
Switching Time Waveforms
1
Thermal Response (Z
thJC
)
D = 0.50
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P
DM
t
1
t
2
Notes:
1. Duty factor D = t
1
/ t
2
2. Peak T
J
= P
DM
x Z
thJC
+ T
C
0.0001
0.001
0.01
0.1
1
0.1
0.01
0.00001
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
