PD-93839C
IRLR8503
IRLR8503
•
•
•
•
N-Channel Application-Specific MOSFET
Ideal for CPU Core DC-DC Converters
Low Conduction Losses
Minimizes Parallel MOSFETs for high current
applications
HEXFET
®
MOSFET for DC-DC Converters
D
• 100% R
G
Tested
Description
This new device employs advanced HEXFET Power
MOSFET technology to achieve very low on-resistance.
The reduced conduction losses makes it ideal for high
efficiency DC-DC converters that power the latest
generation of microprocessors.
The IRLR8503 has been optimized and is 100% tested for
all parameters that are critical in synchronous buck
converters including R
DS(on)
, gate charge and Cdv/dt-
induced turn-on immunity. The IRLR8503 offers an
extremely low combination of Q
sw
& R
DS(on)
for reduced
losses in control FET applications.
The package is designed for vapor phase, infra-red,
convection, or wave soldering techniques. Power
dissipation of greater than 2W is possible in a typical PCB
mount application.
G
S
D-Pak
DEVICE RATINGS (MAX. Values)
IRLR8503
V
DS
R
DS(on)
Q
G
Q
SW
Q
OSS
30V
18 mΩ
20 nC
8 nC
29.5 nC
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain or Source Current
Pulsed Drain Current
T
C
= 25°C
T
C
= 90°C
C
C
Symbol
V
DS
V
GS
I
D
I
DM
= 25°C
= 90°C
P
D
T
J
, T
STG
I
S
I
SM
IRLR8503
30
±20
44
32
196
62
30
-55 to 150
15
196
Units
V
T
Power Dissipation
gÃÃÃÃÃÃÃÃÃÃÃ
T
Junction & Storage Temperature Range
Continuous Source Current (Body Diode)
Pulsed Source Current
A
W
°C
A
Thermal Resistance
Parameter
Maximum Junction-to-Ambient
Maximum Junction-to-Lead
h
eÃh
Symbol
R
θJA
R
θJL
Typ
–––
–––
Max
50
2.0
Units
°C/W
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5/26/05
IRLR8503
Electrical Characteristics
Parameter
Drain-to-Source Breadown Voltage*
Static Drain-Source On-Resistance*
Gate Threshold Voltage*
Drain-Source Leakage Current
Gate-Source Leakage Current*
Total Gate Charge, Control FET*
Total Gate Charge, Synch FET*
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
Switch Charge* (Q
gs2
+ Q
gd
)
Output Charge*
Gate Resistance
Turn-On Delay Time
Drain Voltage Rise Time
Turn-Off Delay Time
Drain Voltage Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Symbol
V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Q
g
Q
g
Q
gs1
Q
gs2
Q
gd
Q
SW
Q
OSS
R
G
t
d(on)
tr
V
t
d(off)
tf
V
C
iss
C
oss
C
rss
Min Typ Max Units
30
–––
–––
1.0
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
0.4
–––
–––
–––
–––
–––
–––
–––
11
13
–––
–––
–––
15
13
3.7
1.3
4.1
5.4
23
–––
10
18
11
3
650
58
–––
16
18
3.0
1.0
150
20
17
–––
–––
–––
8
29.5
1.1
–––
–––
–––
–––
–––
–––
pF
ns
Ω
nC
V
mΩ
V
µA
nA
Conditions
V
GS
= 0V, I
D
= 250µA
V
GS
= 10V, I
D
= 15A
V
GS
= 4.5V, 1
D
= 15A
V
DS
= 30V, V
GS
= 0
V
DS
= 24V, V
GS
= 0, T
J
= 100°C
V
GS
= ± 20V
V
GS
= 5V, I
D
= 15A, V
DS
= 16V
V
GS
= 5V, V
DS
< 100mV
dÃÃÃÃÃÃ
V
DS
= V
GS
, I
D
= 250µA
––– ±100
V
DS
= 16V, I
D
= 15A
V
DS
= 16V, V
GS
= 0
V
DD
= 16V, I
D
= 15A
V
GS
= 5.0V
Clamped Inductive Load
See Test Diagram Fig. 14
V
DS
= 25V
V
GS
= 0
––– 1650 –––
Source-Drain Rating & Characteristics
Parameter
Diode Forward Voltage*
Reverse Recovery Charge
Reverse Recovery Charge
(with Parallel Schottsky)
Symbol
V
SD
Min Typ Max Units
–––
–––
–––
76
1.0
–––
nC
V
I
S
= 15A , V
GS
= 0V
di/dt = 700A/µs
V
DD
= 16V, V
GS
= 0V, I
S
= 15A
di/dt = 700A/µs
(with 10BQ040)
V
DD
= 16V, V
GS
= 0V, I
S
= 15A
d
Conditions
f
Q
rr
f
Q
rr(s)
–––
67
–––
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Calculated continuous current based on maximum allowable
Pulse width
≤
300 µs; duty cycle
≤
2%.
Junction temperature; switching and other losses will
When mounted on 1 inch square copper board, t < 10 sec.
decrease RMS current capability; package limitation
current = 20A.
Typ = measured - Q
oss
R
θ
is measured at T
J
approximately at 90°C
*Devices are 100% tested to these parameters.
2
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IRLR8503
Power MOSFET Optimization for DC-DC Converters
While the IRLR8103V and IRLR8503 can and are be-
ing used in a variety of applications, they were designed
and optimized for low voltage DC-DC conversion in a
synchronous buck converter topology, specifically, mi-
croprocessor power applications. The IRLR8503 (Fig-
ure 1) was optimized for the control FET socket, while
the IRLR8103V was optimized for the synchronous
FET function.
Table 2 – New Charge Parameters
New Charge
Parameter
Q
GS1
Q
GS2
Q
GCONT
Q
SWITCH
Q
OSS
Description
Pre-Threshold Gate Charge
Post-Threshold Gate Charge
Control FET Total Q
G
Charge during control FET switching
Combines Q
GS2
and Q
GD
Output charge
Charge supplied to C
OSS
during the Q
GD
period of control FET switching
Synchronous FET Total Q
G
(V
DS
≤
0)
Figure 5
Figure 6
Figure 4
Figure 3
Waveform
IRLR8503
(Cont FET)
Q
GSYNC
CGD
Drain Voltage
Drain Voltage
CDS
VGTH
QG
(Control FET)
QSwitch
QGD
Gate Voltage
0V
Dead
Time
IRLR8103V
(Sync FET)
CGS
Gate Voltage
VGTH
QG (Sync FET)
0A
Figure 1 – Application
Topology
Figure 2 – Inter-electrode
Capacitance
QGS1
QGS2
Drain Current
Because of the inter-electrode capacitance (Figure 2)
of the Power MOSFET, specifying the R
DSON
of the de-
vice is not enough to ensure good performance. An
optimization between R
DSON
and charge must be per-
formed to insure the best performing MOSFET for a
given application. Both die size and device architec-
ture must be varied to achieve the minimum possible
in-circuit losses. This is independently true for both
control FET and synchronous FET. Unfortunately, the
capacitances of a FET are non-linear and voltage de-
pendent. Therefore, it is inconvenient to specify and
use them effectively in switching power supply power
loss estimations. This was well understood years ago
and resulted in changing the emphasis from capaci-
tance to gate charge on Power MOSFET data sheets.
Table 1 – Traditional Charge Parameters
Device Capacitance
C
GS
C
GS
+ C
GD
C
GD
Corresponding Charge Parameter
Q
GS
Q
G
Q
GD
Body
Diode
Current
Drain Current
Figure 3 – Control FET
Waveform
Figure 4 – Sync FET
Waveform
The waveforms are broken into segments correspond-
ing to charge parameters. These, in turn, correspond
to discrete time segments of the switching waveform.
VIN
g1
N1
Cont FET
Coss1
2n
SN
g2
N2
Sync FET
Coss2
2n
Switch node voltage
(VSN)
N1 Gate
Voltage
N1 Current
N1 Coss Discharge
+
N2 Coss Charge
Figure 5 – Q
OSS
Equivalent Circuit
Figure 6 – Q
OSS
Waveforms
International Rectifier has recently taken the industry
a step further by specifying new charge parameters
that are even more specific to DC-DC converter de-
sign (Table 2). In order to understand these parameters,
it is best to start with the in-circuit waveforms in Fig-
ure 3 & Figure 4.
Losses may be broken into four categories: conduc-
tion loss, gate drive loss, switching loss, and output
loss. The following simplified power loss equation is
true for both MOSFETs in a synchronous buck con-
verter:
P
LOSS
= P
CONDUCTION
+ P
GATE DRIVE
+ P
SWITCH
+ P
OUTPUT
For the synchronous FET, the P
SWITCH
term becomes
virtually zero and is ignored.
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IRLR8503
Table 3 and Table 4 describes the event during the various charge segments and shows an approximation of losses during that
period.
Table 3 – Control FET Losses
Description
Segment Losses
2
Conduction Losses associated with MOSFET on time. I
RMS
is a function of load
P
COND
=
I
RMS
×
R
DS (on )
current and duty cycle.
Loss
Gate Drive Losses associated with charging and discharging the gate of the
P
IN
=
V
G
×
Q
G
× ƒ
MOSFET every cycle. Use the control FET Q
G
.
Loss
Switching Losses during the drain voltage and drain current transitions for every full cycle.
Q
GS
2
׃
Losses occur during the Q
GS2
and Q
GD
time period and can be simplified by using
P
QGS
2
≈
V
IN
×
I
L
×
Loss
I
G
Q
switch
.
Q
P
QGD
≈
V
IN
×
I
L
×
GD
× ƒ
I
G
P
SWITCH
≈
V
IN
×
I
L
Q
SW
׃
I
G
Output
Loss
Losses associated with the Q
OSS
of the device every cycle when the control
Q
FET turns on. Losses are caused by both FETs, but are dissipated by the control
P
OUTPUT
=
OSS
×
V
IN
×
F
2
FET.
Table 4 – Synchronous FET Losses
Description
Losses associated with MOSFET on time. I
RMS
is a function of load current and
duty cycle.
Losses associated with charging and discharging the gate of the MOSFET every
cycle. Use the Sync FET Q
G
.
Generally small enough to ignore except at light loads when the current reverses
in the output inductor. Under these conditions various light load power saving
techniques are employed by the control IC to maintain switching losses to a
negligible level.
Segment Losses
Conduction
Loss
Gate Drive
Loss
Switching
Loss
P
COND
=
I
RMS
×
R
DSon
2
P
IN
=
V
G
×
Q
G
× ƒ
P
SWITCH
≈
0
Output
Loss
Losses associated with the Q
OSS
of the device every cycle when the control FET
Q
turns on. They are caused by the synchronous FET, but are dissipated in the control
P
OUTPUT
=
OSS
×
V
IN
× ƒ
2
FET.
Typical PC Application
The IRLR8103V and the IRLR8503 are suitable for
Synchronous Buck DC-DC Converters, and are optimized
for use in next generation CPU applications. The
IRLR8103V is primarily optimized for use as the low side
synchronous FET (Q2) with low R
DS(on)
and high CdV/dt
immunity.The IRLR8503 is primarily optimized for use as
the high side control FET (Q2) with low cobmined Qsw and
R
DS(on)
, but can also be used as a synchronous FET. The
IRLR8503 is also tested for Cdv/dt immunity, critical for
the low side socket. The typical configuration in which
these devices may be used in shown in Figure 7.
IRLR8503
Control FET (Q1)
1 x IRLR8103
V
or
or
2 x IRLR8503
Synchronous
FET (Q2)
Figure 7. 2 & 3-FET solution for
Synchronous Buck Topology.
4
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IRLR8503
2.5
Typical Characteristics
IRLR8503
6.0
ID = 15A
VGS, Gate-to-Source Voltage (V)
RDS(on) , Drain-to-Source On Resistance
ID = 15A
VDS = 20V
VGS = 4.5V
2.0
4.0
(Normalized)
1.5
2.0
1.0
0.5
-60 -40 -20
0
20
40
60
80 100 120 140 160
0.0
0
4
8
12
16
T J , Junction Temperature ( °C )
QG, Total Gate Charge (nC)
Figure 8. Normalized On-Resistance vs. Temperature
RDS(on) , Drain-to -Source On Resistance (Ω)
0.015
Figure 9. Gate-to-Source Voltage vs. Typical Gate
Charge
2500
0.014
2000
V
GS
C
iss
C
rss
C
oss
=
=
=
=
0V,
f = 1MHz
C
gs
+ C
gd ,
C
ds
SHORTED
C
gd
C
ds
+ C
gd
C, Capacitance (pF)
0.013
Ciss
1500
0.012
1000
ID = 15A
0.011
Coss
500
0.010
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0 11.0 12.0
0
Crss
1
10
100
VGS, Gate -to -Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage
100
1000.0
Figure 11. Typical Capacitance vs. Drain-to-Source Voltage
ID, Drain-to-Source Current
(Α
)
100.0
T J = 150°C
10.0
T J = 25°C
VDS = 15V
1.0
2.5
3.0
3.5
20µs PULSE WIDTH
4.0
4.5
5.0
5.5
VGS, Gate-to-Source Voltage (V)
Figure 12. Typical Transfer Characteristics
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