Data Sheet No. PD60017 Rev.Q
IR2125
(S) & (PbF)
CURRENT LIMITING SINGLE CHANNEL DRIVER
Features
•
Floating channel designed for bootstrap operation
Fully operational to +500V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 12 to 18V
Undervoltage lockout
Current detection and limiting loop to limit driven
power transistor current
Error lead indicates fault conditions and programs
shutdown time
Output in phase with input
2.5V, 5V and 15V input logic compatible
Also available LEAD-Free
Product Summary
V
OFFSET
I
O
+/-
V
OUT
V
CSth
t
on/off
(typ.)
500V max.
1A / 2A
12 - 18V
230 mV
150 & 150 ns
•
•
•
•
•
•
•
Packages
Description
The IR2125(S) is a high voltage, high speed power
MOSFET and IGBT driver with over-current limiting
protection circuitry. Proprietary HVIC and latch im-
mune CMOS technologies enable ruggedized mono-
lithic construction. Logic inputs are compatible with
16-Lead SOIC
8-Lead PDIP
standard CMOS or LSTTL outputs, down to 2.5V
(Wide Body)
logic. The output driver features a high pulse current
buffer stage designed for minimum driver cross-conduction. The protection circuitry detects over-current in the
driven power transistor and limits the gate drive voltage. Cycle by cycle shutdown is programmed by an external
capacitor which directly controls the time interval between detection of the over-current limiting conditions and
latched shutdown. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high
or low side configuration which operates up to 500 volts.
Typical Connection
up to 500V
V
CC
IN
V
CC
IN
ERR
COM
V
B
HO
CS
V
S
TO
LOAD
(Refer to Lead Assignments
for correct pin configura-
tion). This/These diagram(s)
show electrical connections
only. Please refer to our
Application Notes and
DesignTips for proper circuit
board layout.
www.irf.com
1
IR2125
(S) & (PbF)
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
IN
V
ERR
V
CS
dV
s
/dt
P
D
Rth
JA
T
J
T
S
T
L
Definition
High Side Floating Supply Voltage
High Side Floating Offset Voltage
High Side Floating Output Voltage
Logic Supply Voltage
Logic Input Voltage
Error Signal Voltage
Current Sense Voltage
Allowable Offset Supply Voltage Transient
Package Power Dissipation @ T
A
≤
+25°C (8 lead PDIP)
(16 lead SOIC)
Thermal Resistance, Junction to Ambient
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
(8 lead PDIP)
(16lLead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
-0.3
V
S
- 0.3
—
—
—
—
—
—
-55
—
Max.
525
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
V
B
+ 0.3
50
1.0
1.25
125
100
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at 15V differential.
Symbol
V
B
V
S
V
HO
V
CC
V
IN
V
ERR
V
CS
T
A
Definition
High Side Floating Supply Voltage
High Side Floating Offset Voltage
High Side Floating Output Voltage
Logic Supply Voltage
Logic Input Voltage
Error Signal Voltage
Current Sense Signal Voltage
Ambient Temperature
Min.
V
S
+ 12
Note 1
V
S
0
0
0
V
S
-40
Max.
V
S
+ 18
500
V
B
18
V
CC
V
CC
V
B
125
Units
V
°C
Note 1:
Logic operational for V
S
of -5 to +500V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
2
www.irf.com
IR2125
(S) & (PbF)
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 3300 pF and T
A
= 25°C unless otherwise specified. The dynamic electrical characteristics
are measured using the test circuit shown in Figures 3 through 6.
Symbol
t
on
t
off
t
sd
t
r
t
f
t
cs
t
err
Definition
Turn-On Propagation Delay
Turn-Off Propagation Delay
ERR Shutdown Propagation Delay
Turn-On Rise Time
Turn-Off Fall Time
CS Shutdown Propagation Delay
CS to ERR Pull-Up Propagation Delay
Figure Min. Typ. Max. Units Test Conditions
7
8
9
10
11
12
13
—
—
—
—
—
—
—
170
200
1.7
43
26
0.7
9.0
240
270
2.2
60
35
1.2
12
ns
µs
ns
µs
V
IN
= 0 & 5V
V
S
= 0 to 600V
C
ERR
= 270 pF
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V and T
A
= 25°C unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to
COM. The V
O
and I
O
parameters are referenced to V
S
.
Symbol
V
IH
V
IL
V
CSTH+
V
CSTH-
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
I
CS+
I
CS-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
ERR
I
ERR+
I
ERR-
I
O+
I
O-
Definition
Logic “1” Input Voltage
Logic “0” Input Voltage
CS Input Positive Going Threshold
CS Input Negative Going Threshold
High Level Output Voltage, V
BIAS
- V
O
Low Level Output Voltage, V
O
Offset Supply Leakage Current
Quiescent V
BS
Supply Current
Quiescent V
CC
Supply Current
Logic “1” Input Bias Current
Logic “0” Input Bias Current
“High” CS Bias Current
“Low” CS Bias Current
V
BS
Supply Undervoltage Positive Going
Threshold
V
BS
Supply Undervoltage Negative Going
Threshold
V
CC
Supply Undervoltage Positive Going
Threshold
V
CC
Supply Undervoltage Negative Going
Threshold
ERR Timing Charge Current
ERR Pull-Up Current
ERR Pull-Down Current
Output High Short Circuit Pulsed Current
Output Low Short Circuit Pulsed Current
Figure Min. Typ. Max. Units Test Conditions
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
2.2
—
150
130
—
—
—
—
—
—
—
—
—
8.5
7.7
8.3
7.3
65
8.0
16
1.0
2.0
—
—
230
210
—
—
—
400
700
4.5
—
4.5
—
9.2
8.3
8.9
8.0
100
15
30
1.6
3.3
—
0.8
320
300
100
100
50
1000
1200
10
1.0
10
1.0
10.0
9.0
9.6
8.7
130
—
mA
—
—
A
—
µA
V
IN
= 5V, V
CS
= 3V
ERR < V
ERR+
V
IN
= 5V, V
CS
= 3V
ERR > V
ERR+
V
IN
= 0V
V
O
= 0V, V
IN
= 5V
PW
≤
10
µs
V
O
= 15V, V
IN
= 0V
PW
≤
10
µs
V
V
mV
I
O
= 0A
I
O
= 0A
V
B
= V
S
= 500V
V
IN
= V
CS
= 0V or 5V
V
IN
= V
CS
= 0V or 5V
V
IN
= 5V
V
IN
= 0V
V
CS
= 3V
V
CS
= 0V
µA
www.irf.com
3
IR2125
(S) & (PbF)
Functional Block Diagram
V
CC
UV
DETECT
UP
SHIFTERS
IN
1.8V
LATCHED
SHUTDOWN
PULSE
GEN
V
B
0.23V
ERROR
TIMING
ERR
Q
R
S
PULSE
FILTER
PULSE
GEN
DOWN
SHIFTERS
-
+
AMPLIFER
blanking
filter
COMPARATOR
CS
UV
DETECT
HV
LEVEL
SHIFT
V
B
PRE
DRIVER
BUFFER
R
R
S
Q
PULSE
FILTER
HO
V
S
1.8V
COM
HV
LEVEL
SHIFT
Lead Definitions
Symbol
V
CC
IN
ERR
COM
V
B
HO
V
S
CS
Description
Logic and gate drive supply
Logic input for gate driver output (HO), in phase with HO
Serves multiple functions; status reporting, linear mode timing and cycle by cycle logic
shutdown
Logic ground
High side floating supply
High side gate drive output
High side floating supply return
Current sense input to current sense comparator
Lead Assignments
1
1
2
3
4
V
CC
IN
ERR
COM
V
B
HO
CS
V
S
8
7
6
5
Vcc
IN
ERR
COM
VB
16
15
2
3
4
5
6
7
8
HO
14
CS
13
VS
12
11
10
9
8 Lead PDIP
IR2125
4
Part Number
16 Lead SOIC (Wide Body)
IR2125S
www.irf.com
IR2125
(S) & (PbF)
HV=10 to 600V
ERR
t sd
HO
www.irf.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
