Data Sheet No. PD60162 Rev. W
IR2106(4)(S) & (PbF)
HIGH AND LOW SIDE DRIVER
Features
•
Floating channel designed for bootstrap operation
•
•
•
•
•
•
•
•
Packages
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V (IR2106(4))
Undervoltage lockout for both channels
3.3V, 5V and 15V input logic compatible
Matched propagation delay for both channels
Logic and power ground +/- 5V offset.
Lower di/dt gate driver for better noise immunity
Outputs in phase with inputs (IR2106)
Also available LEAD-FREE
8-Lead SOIC
8-Lead PDIP
14-Lead SOIC
14-Lead PDIP
Description
2106/2301//2108//2109/2302/2304
Feature Comparison
Cross-
The IR2106(4)(S) are high voltage,
Input
conduction
Dead-Time
Ground Pins
Ton/Toff
Part
high speed power MOSFET and
prevention
logic
IGBT drivers with independent high
logic
2106/2301
COM
and low side referenced output chan-
HIN/LIN
no
none
220/200
21064
VSS/COM
nels. Proprietary HVIC and latch
2108
Internal 540ns
COM
HIN/LIN
yes
220/200
immune CMOS technologies enable
Programmable 0.54~5
µs
21084
VSS/COM
2109/2302
Internal 540ns
COM
ruggedized monolithic construction.
IN/SD
yes
750/200
Programmable 0.54~5
µs
21094
VSS/COM
The logic input is compatible with
yes
160/140
Internal 100ns
HIN/LIN
COM
2304
standard CMOS or LSTTL output,
down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high
side configuration which operates up to 600 volts.
Typical Connection
V
CC
up to 600V
V
CC
HIN
LIN
V
B
HO
V
S
LO
TO
LOAD
HIN
LIN
COM
IR2106
HO
V
CC
HIN
up to 600V
V
CC
HIN
LIN
V
B
V
S
TO
LOAD
(Refer to Lead Assignments for cor-
rect pin configuration). This/These
diagram(s) show electrical connec-
tions only. Please refer to our Appli-
cation Notes and DesignTips for
proper circuit board layout.
LIN
IR21064
COM
LO
V
SS
V
SS
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1
IR2106(4)
(S) & (PBF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
V
SS
dV
S
/dt
P
D
Definition
High side floating absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage
Logic ground (IR21064 only)
Allowable offset supply voltage transient
Package power dissipation @ T
A
≤
+25°C
(8 lead PDIP)
(8 lead SOIC)
(14 lead PDIP)
(14 lead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
V
SS
- 0.3
V
CC
- 25
—
—
—
—
—
—
—
—
—
—
-50
—
Max.
625
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
50
1.0
0.625
1.6
1.0
125
200
75
120
150
150
300
Units
V
V/ns
W
Rth
JA
Thermal resistance, junction to ambient
(8 lead PDIP)
(8 lead SOIC)
(14 lead PDIP)
(14 lead SOIC)
°C/W
T
J
T
S
T
L
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
°C
2
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IR2106(4)
(S & (PbF))
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V
S
and V
SS
offset rating are tested with all supplies biased at 15V differential.
Symbol
VB
V
S
V
HO
V
CC
V
LO
V
IN
V
SS
T
A
Definition
High side floating supply absolute voltage IR2106(4)
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage IR2106(4)
Low side output voltage
Logic input voltage
Logic ground (IR21064 only)
Ambient temperature
Min.
V
S
+ 10
Note 1
V
S
10
0
V
SS
-5
-40
Max.
V
S
+ 20
600
V
B
20
V
CC
V
CC
5
125
Units
V
°C
Note 1: Logic operational for V
S
of -5 to +600V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, V
SS
= COM, C
L
= 1000 pF, T
A
= 25°C.
Symbol
ton
toff
MT
tr
tf
Definition
Turn-on propagation delay
Turn-off propagation delay
Delay matching, HS & LS turn-on/off
Turn-on rise time
Turn-off fall time
Min.
—
—
—
—
—
Typ.
220
200
0
150
50
Max. Units Test Conditions
300
280
30
220
80
nsec
V
S
= 0V
V
S
= 0V
V
S
= 0V
V
S
= 0V or 600V
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3
IR2106(4)
(S) & (PBF)
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, V
SS
= COM and T
A
= 25°C unless otherwise specified. The V
IL
, V
IH
and I
IN
parameters are
referenced to V
SS
/COM and are applicable to the respective input leads. The V
O
, I
O
and Ron parameters are referenced to
COM and are applicable to the respective output leads: HO and LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
CCUV+
V
BSUV+
V
CCUV-
V
BSUV-
V
CCUVH
V
BSUVH
I
O+
I
O-
Definition
Logic “1” input voltage (IR2106(4))
Logic “0” input voltage (IR2106(4))
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
V
IN
= 5V (IR2106(4))
Logic “0” input bias current
V
IN
= 0V (IR2106(4))
V
CC
and V
BS
supply undervoltage positive going
threshold
V
CC
and V
BS
supply undervoltage negative going
threshold
Hysteresis
Output high short circuit pulsed current
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
2.9
—
—
—
—
20
60
—
—
0.8
0.3
—
75
120
—
0.8
1.4
0.6
50
130
180
µA
—
—
8.0
7.4
0.3
120
250
5
—
8.9
8.2
0.7
200
350
20
2
9.8
9.0
—
—
mA
—
V
O
= 0V,
PW
≤
10
µs
V
O
= 15V,
PW
≤
10
µs
V
V
CC
= 10V to 20V
V
CC
= 10V to 20V
I
O
= 20 mA
I
O
= 20 mA
V
B
= V
S
= 600V
V
IN
= 0V or 5V
V
IN
= 0V or 5V
V
4
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IR2106(4)
(S & (PbF))
Functional Block Diagrams
VB
IR2106
HV
LEVEL
SHIFTER
PULSE
GENERATOR
UV
DETECT
R
PULSE
FILTER
R
S
Q
HO
HIN
VSS/COM
LEVEL
SHIFT
VS
VCC
UV
DETECT
LO
LIN
VSS/COM
LEVEL
SHIFT
DELAY
COM
VB
IR21064
HV
LEVEL
SHIFTER
PULSE
GENERATOR
UV
DETECT
R
PULSE
FILTER
R
S
Q
HO
HIN
VSS/COM
LEVEL
SHIFT
VS
VCC
UV
DETECT
LO
LIN
VSS/COM
LEVEL
SHIFT
DELAY
COM
VSS
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5
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