Core V2.0 Handbook
Table of Contents
Introduction ....................................................................................................................3
General Description ....................................................................................................................................... 3
Key Features ................................................................................................................................................. 5
Supported Families ........................................................................................................................................ 5
Core Version .................................................................................................................................................. 5
Utilization and Performance .......................................................................................................................... 5
Theory of Operations ..................................................................................................................................... 8
Interface Description .................................................................................................................................... 13
Implementation Details ................................................................................................................................ 21
Decimation Filter Timing .............................................................................................................................. 23
Interpolation Filter Timing ............................................................................................................................ 26
References .................................................................................................................................................. 29
List of Changes ............................................................................................................ 31
Product Support........................................................................................................... 33
Customer Service ........................................................................................................................................ 33
Customer Technical Support Center ........................................................................................................... 33
Technical Support ........................................................................................................................................ 33
Website ........................................................................................................................................................ 33
Contacting the Customer Technical Support Center ................................................................................... 33
ITAR Technical Support .............................................................................................................................. 34
CoreCIC v2.0 Handbook
2
Introduction
General Description
Microsemi
CoreCIC IP is a highly configurable RTL generator for the decimation or interpolation cascaded
integrator-comb (CIC) filters. The CIC filters are widely used in multi-rate signal processing, particularly in up-
converters and down-converters, modulators and demodulators, sigma-delta analog to digital converters, and so on.
These filters are popular in decimation and interpolation filters where substantial rate change factor is required. The
CIC filters provide a linear phase response.
CoreCIC v2.0 Handbook
3
Key Features
Key Features
CoreCIC supports decimation and interpolation filter types. Following are the key features of CoreCIC filter:
•
Fixed or programmable rate change from 2 to 1024
•
One to eight integrator-comb stages
•
Comb differential delay of one or two
•
Signed 2's complement input data
•
Input data width from 1 to 32 bits
•
Output data width up to 100 bits
•
Choice of output data truncation and two rounding types
•
Optional Hogenauer pruning
•
Support for up to 64 channels
Supported Families
CoreCIC supports the following families:
•
SmartFusion
2
•
IGLOO
2
•
RTG4™
Core Version
This handbook applies to CoreCIC v2.0.
Utilization and Performance
The resource utilization and core performance are shown on
Table 1
and
Table 2
for SmartFusion2 M2S050 device,
speed grade -1.
Table 1
CIC Decimator Resource Utilization and Performance
Configuration
Channels per IF
Number of IF
Rate Change
Factor
Output Data
Width
Number of
Stages
Resource Utilization
RAM 64x18
RAM 1K18
Maximum
Clock
Rate,
MHz
4LUT
RAM blocks are not used; Differential Delay = 1
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
4
4
4
40
40
40
4
4
3
3
3
3
3
3
2
2
1
4
1
1
4
1
1
4
1
1
5
1
1
5
1
1
751
1,905
1,452
1,063
2,713
2,030
511
1,241
730
1,902
1,706
1,022
2,702
2,388
495
1,224
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
385
345
314
341
331
313
386
366
CoreCIC v2.0 Handbook
Input Data
Width
DFF
5
FPGA/CPLD
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