74AUP2G32
Rev. 8 — 3 July 2017
Low-power dual 2-input OR gate
Product data sheet
1
General description
The 74AUP2G32 provides dual 2-input OR function.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2
Features and benefits
•
Wide supply voltage range from 0.8 V to 3.6 V
•
High noise immunity
•
Complies with JEDEC standards:
–
JESD8-12 (0.8 V to 1.3 V)
–
JESD8-11 (0.9 V to 1.65 V)
–
JESD8-7 (1.2 V to 1.95 V)
–
JESD8-5 (1.8 V to 2.7 V)
–
JESD8-B (2.7 V to 3.6 V)
•
ESD protection:
–
HBM JESD22-A114F Class 3A exceeds 5000 V
–
MM JESD22-A115-A exceeds 200 V
–
CDM JESD22-C101E exceeds 1000 V
•
Low static power consumption; I
CC
= 0.9 μA (maximum)
•
Latch-up performance exceeds 100 mA per JESD 78 Class II
•
Inputs accept voltages up to 3.6 V
•
Low noise overshoot and undershoot < 10 % of V
CC
•
I
OFF
circuitry provides partial Power-down mode operation
•
Multiple package options
•
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
Low-power dual 2-input OR gate
74AUP2G32
3
Ordering information
Package
Temperature
range
Name
VSSOP8
XSON8
XSON8
XQFN8
XSON8
XSON8
X2SON8
Table 1. Ordering information
Type number
Description
Version
74AUP2G32DC
74AUP2G32GT
74AUP2G32GF
74AUP2G32GM
74AUP2G32GN
74AUP2G32GS
74AUP2G32GX
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 x 1.95 x 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
plastic thermal enhanced extremely thin small outline
package; no leads; 8 terminals;
body 1.35 x 0.8 x 0.35 mm
SOT1089
SOT902-2
SOT1116
SOT1203
SOT1233
4
Marking
Marking code
p32
p32
pG
p32
pG
pG
pG
[1]
Table 2. Marking codes
Type number
74AUP2G32DC
74AUP2G32GT
74AUP2G32GF
74AUP2G32GM
74AUP2G32GN
74AUP2G32GS
74AUP2G32GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74AUP2G32
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 3 July 2017
2 / 22
Nexperia
Low-power dual 2-input OR gate
74AUP2G32
5
Functional diagram
≥1
1A
1B
2A
2B
1Y
B
2Y
≥1
A
Y
mna166
001aah791
001aah792
Figure 1. Logic symbol
Figure 2. IEC logic symbol
Figure 3. Logic diagram (one gate)
6
Pinning information
6.1 Pinning
74AUP2G32
1A
1
8
V
CC
1B
2
7
1Y
74AUP2G32
1A
1B
2Y
GND
1
2
3
4
001aae359
2Y
3
6
2B
8
7
6
5
V
CC
1Y
2B
2A
GND
4
5
2A
001aae360
Transparent top view
Figure 4. Pin configuration SOT765-1
Figure 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP2G32
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 3 July 2017
3 / 22
Nexperia
Low-power dual 2-input OR gate
74AUP2G32
74AUP2G32
terminal 1
index area
1Y
1
V
CC
7
1A
74AUP2G32
1A 1
7
8
V
CC
1B
2
4
GND
2Y
3
5
aaa-027034
8
1Y
2B
2
6
1B
6
2B
4
2A
3
5
2Y
GND
2A
001aae361
Transparent top view
Transparent top view
Figure 6. Pin configuration SOT902-2
Figure 7. Pin configuration SOT1233
6.2 Pin description
Table 3. Pin description
Symbol
Pin
SOT765-1, SOT833-1, SOT1089, SOT1116,
SOT1203 and SOT1233
SOT902-2
7, 3
6, 2
4
1, 5
8
Description
1A, 2A
1B, 2B
GND
1Y, 2Y
V
CC
1, 5
2, 6
4
7, 3
8
data input
data input
ground (0 V)
data output
supply voltage
7
Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
nA
L
L
H
H
Output
nB
L
H
L
H
nY
L
H
H
H
74AUP2G32
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 3 July 2017
4 / 22
Nexperia
Low-power dual 2-input OR gate
74AUP2G32
8
Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
-0.5
-50
-0.5
-50
[1]
Max
+4.6
-
+4.6
-
+4.6
±20
+50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
-0.5
-
-
-50
-65
T
amb
= -40 °C to +125 °C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110 °C the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 °C the value of P
tot
derates linearly with 7.8 mW/K.
For X2SON8 package: above 118 °C the value of P
tot
derates linearly with 7.7 mW/K.
9
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Table 6. Operating conditions
Symbol
V
CC
V
I
V
O
T
amb
Δt/ΔV
Conditions
Min
0.8
0
0
0
-40
0
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
°C
ns/V
74AUP2G32
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 3 July 2017
5 / 22
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