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74AVCH16T245
16-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 5 — 1 March 2012
Product data sheet
1. General description
The 74AVCH16T245 is a 16-bit transceiver with bidirectional level voltage translation and
3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit
transceiver. It has dual supplies (V
CC(A)
and V
CC(B)
) for voltage translation and four 8-bit
input-output ports (nAn, nBn) each with its own output enable (nOE) and send/receive
(nDIR) input for direction control. V
CC(A)
and V
CC(B)
can be independently supplied at any
voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation
between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH
on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission
from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance
OFF-state
The device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both A and B outputs are in the high-impedance OFF-state. The bus-hold
circuitry on the powered-up side always stays active.
The 74AVCH16T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 0.8 V to 3.6 V
V
CC(B)
: 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101D exceeds 1000 V
Maximum data rates:
380 Mbit/s ( 1.8 V to 3.3 V translation)
NXP Semiconductors
74AVCH16T245
16-bit dual supply translating transceiver; 3-state
200 Mbit/s ( 1.1 V to 3.3 V translation)
200 Mbit/s ( 1.1 V to 2.5 V translation)
200 Mbit/s ( 1.1 V to 1.8 V translation)
150 Mbit/s ( 1.1 V to 1.5 V translation)
100 Mbit/s ( 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AVCH16T245DGG
40 C
to +125
C
74AVCH16T245DGV
74AVCH16T245EV
74AVCH16T245BX
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
TSSOP48
Description
Version
plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
Type number
TSSOP48
[1]
plastic thin shrink small outline package; 48 leads; SOT480-1
body width 4.4 mm; lead pitch 0.4 mm
VFBGA56
HXQFN60
plastic very thin fine-pitch ball grid array package; SOT702-1
56 balls; body 4.5
7
0.65 mm
plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4
6
0.5 mm
SOT1134-2
[1]
Also known as TVSOP48.
4. Functional diagram
1DIR
1OE
2DIR
2OE
1A1
1B1
V
CC(A)
V
CC(B)
2A1
2B1
V
CC(A)
V
CC(B)
001aak426
to other seven channels
to other seven channels
Fig 1.
Logic diagram
74AVCH16T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 1 March 2012
2 of 29
NXP Semiconductors
74AVCH16T245
16-bit dual supply translating transceiver; 3-state
1B1
V
CC(A)
V
CC(B)
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1OE
1DIR
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2B1
V
CC(A)
V
CC(B)
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2OE
2DIR
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
001aak425
Fig 2.
Logic symbol
74AVCH16T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 1 March 2012
3 of 29
NXP Semiconductors
74AVCH16T245
16-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
74AVCH16T245
1DIR
1B1
1B2
GND
1B3
1B4
V
CC(B)
1B5
1B6
1
2
3
4
5
6
7
8
9
48 1OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 V
CC(A)
41 1A5
40 1A6
39 GND
38 1A7
37 1A8
36 2A1
35 2A2
34 GND
33 2A3
32 2A4
31 V
CC(A)
30 2A5
29 2A6
28 GND
27 2A7
26 2A8
25 2OE
001aak430
GND 10
1B7 11
1B8 12
2B1 13
2B2 14
GND 15
2B3 16
2B4 17
V
CC(B)
18
2B5 19
2B6 20
GND 21
2B7 22
2B8 23
2DIR 24
ball A1
74AVCH16T245
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
001aak431
Transparent top view
Fig 3. Pin configuration SOT362-1 and SOT480-1
(TSSOP48)
Fig 4.
Pin configuration SOT702-1 (VFBGA56)
74AVCH16T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 1 March 2012
4 of 29
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