The PL680-3X is a monolithic low jitter and low phase
noise high performance clock, capable of producing
0.4ps RMS phase jitter and LVCMOS, LVDS or LVPECL
outputs, covering a wide frequency output range up to
640MHz. It allows high performance and high frequency
output, using a low cost fundamental crystal of 19MHz to
40MHz.
The frequency selector pads of PL680-3X enable output
frequencies of (2, 4, 8, or 16) * F
XIN
. The PL680-3X is
designed to address the demanding requirements of high
performance applications such Fiber Channel, serial ATA,
Ethernet, SAN, etc.
OE_CTRL
DNC
PL680-3X
2
3
4
5
GNDANA
3x3 QFN
Note1: QBAR is used for single ended CMOS output.
Note2: ^ Denotes 60kΩ internal pull up resistor.
BLOCK DIAGRAM
SEL[0:2]
VCO
Divider
XIN
XOUT
Xtal
Osc
Phase
Detector
Charge Pump
+
Loop Filter
VCO
(F
XiN
x16)
Output
Divider
(1,2,4,8)
GNDBUF
LM
LP
QBAR
Q
Performance Tuner
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/14/07 Page 1
38-640MHz Low Phase Noise XO
OUTPUT ENABLE LOGIC LEVELS
Part #
PL680-38 (LVPECL)
PL680-37 & 39 (LVCMOS or LVDS)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
PIN DESCRIPTIONS
Name
VDDANA
XIN
XOUT
SEL2
OE_CTRL
DNC
GNDANA
LP
LM
GNDBUF
Q
VDDBUF
QBAR
GNDBUF
SEL1
SEL0
TSSOP-16L
Pin number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
QFN-16L
Pin number
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
Type
P
I
O
I
I
-
P
-
-
P
O
P
O
P
I
I
Description
VDD for analog Circuitry.
Crystal input pin. (See Crystal Specifications on page 4).
Crystal output pin. (See Crystal Specifications on page 4).
Output frequency Selector pin.
Output enable control pin. (See OUTPUT ENABLE LOGIC
LEVELS above).
Do Not Connect
Ground for analog circuitry.
Tuning inductor connection. The inductor is recommended
to be a high Q small size 0402 or 0603 SMD component,
and must be placed between LP and adjacent LM pin.
Place inductor as close to the IC as possible to minimize
parasitic effects and to maintain inductor Q.
GND connection for output buffer circuitry.
LVPECL or LVDS output.
VDD connection for output buffer circuitry. VDDBUF
should be separately decoupled from other VDDs whenever
possible.
Complementary LVPECL, LVDS output; Or single ended
LVCMOS output.
GND connection for output buffer circuitry.
Output frequency Selector pin.
Output frequency Selector pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/14/07 Page 2
38-640MHz Low Phase Noise XO
FREQUENCY SELECTION TABLE
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Selected Multiplier/Output Frequency
VCO Max*
VCO Min*
Reserved
Reserved
Fin x 2
Fin x 8
Fin x 16
Fin x 4
All SEL pads have a 60kΩ internal pull-up resistor (default value is ‘1’). Bond to GND to set to 0.
* Special Test Modes to help selecting the inductor value for the target output frequency.
PERFORMANCE TUNING & INDUCTOR VALUE SELECTION
Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor
values. In addition, the chart below could be used as a reference for quick inductor value selection.
Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max”
represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output
frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are
around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency
is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock
in the middle of its tuning range with maximum margin on either side.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/14/07 Page 3
38-640MHz Low Phase Noise XO
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
-0.5
-0.5
-65
-40
MIN.
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
UNITS
V
V
V
C
C
C
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.* Operating Temperature is guaranteed by design for all parts
(COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator
Frequency
Crystal Loading Rating
Crystal Shunt Capacitance
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0 (xtal)
R
E
AT cut
CONDITIONS
Parallel Fundamental Mode, 3.3V
Parallel Fundamental Mode, 2.5V
MIN.
19
19
18
5
30
TYP.
MAX.
40
28.125
UNITS
MHz
pF
pF
Ω
Note:
Crystal Loading rating: 18 pF is the loading the crystal sees from the XO chip. It is assumed that the crystal will be at nominal frequency at this
load. If the crystal requires less load to be at nominal frequency, then a capacitor can placed in series with the crystal. If the crystal requires more
load to be at nominal frequency, capacitors can be placed from XIN and XOUT to ground. This however may reduce the oscillator gain.
3. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic
(Loaded Outputs)
Operating Voltage
Output Clock
Duty Cycle
Short Circuit Current
Stabilization Time *
T
STB
From power valid
SYMBOL
I
DD
V
DD
@ 50% V
DD
(LVCMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (LVPECL)
CONDITIONS
LVPECL/LVDS 38MHz<F
OUT
<100MHz
/LVCMOS
100MHz<F
OUT
<320MHz
LVPECL/LVDS 320MHz<F
OUT
<640MHz
2.25**
45
50
50
10
MIN.
TYP.
MAX.
65/45/30
80/60/40
90/70
3.63
55
V
%
mA
ms
mA
UNITS
Note:
CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load. Parameters denoted with an asterisk (*) represent
nominal characterization data and are not production tested to any specific limits. The 2.5V operating supply voltage, denoted by (**), is limited to a
maximum VCO frequency of 450 MHz.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/14/07 Page 4
38-640MHz Low Phase Noise XO
4. Jitter Specifications
PARAMETERS
CONDITIONS
FREQUENCY
106.25MHz
Integrated jitter
RMS
156.25MHz
Integrated 12kHz to 20MHz
212.5MHz
312.5MHz
622.08MHz
106.25MHz
Period jitter
RMS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
156.25MHz
212.5MHz
312.5MHz
622.08MHz
106.25MHz
Period jitter
Peak-to-Peak
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
156.25MHz
212.5MHz
312.5MHz
622.08MHz
5. Phase Noise Specifications
PARAMETERS
FREQ.
106.25MHz
Phase Noise
relative to
carrier (typical)
156.25MHz
212.5MHz
312.5MHz
622.08MHz
@10Hz
-66
-62
-62
-59
-49
@100Hz
-96
-92
-92
-85
-84
@1kHz
-122
-120
-118
-117
-111
@10kHz
-132
-132
-126
-128
-120
@100kHz
-126
-128
-120
-125
-118
@1M
-144
-140
-140
-139
-128
@10M
-150
-150
-150
-148
-138
dBc/Hz
UNITS
MIN.
TYP.
0.4
0.4
0.4
0.4
0.4
3
3
3
3
6
20
20
20
20
40
MAX.
0.5
0.5
0.5
0.5
0.5
5
5
5
5
8
30
30
30
30
50
ps
ps
ps
UNITS
6. LVCMOS Electrical Characteristics
PARAMETERS
Output Drive Current
Output Clock Rise/Fall Time
SYMBOL
I
OH
I
OL
T
R
/T
F
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
20%-80% with 50Ω Load
MIN.
30
30
0.7
0.3
TYP.
MAX.
UNITS
mA
mA
ns
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
1.Warning: Can't display state machine states -- register holding state machine bit "|times|t_state.t0" was synthesized away
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