(fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table 3). It also offers I/O
safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices
do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/Os, a programmable
power-down mode for extra power savings and individual output slew rate control for the highest speed
transition or for the lowest noise transition.
Table 3. ispMACH 4A Package and I/O Options (Number of I/Os and dedicated inputs in Table)
3.3 V Devices
Package
44-pin PLCC
44-pin TQFP
48-pin TQFP
100-pin TQFP
100-pin PQFP
100-ball caBGA
144-pin TQFP
144-ball fpBGA
208-pin PQFP
256-ball fpBGA
256-ball BGA
388-ball fpBGA
5 V Devices
Package
44-pin PLCC
44-pin TQFP
48-pin TQFP
100-pin TQFP
100-pin PQFP
144-pin TQFP
208-pin PQFP
M4A5-32
32+2
32+2
32+2
M4A5-64
32+2
32+2
32+2
48+8
64+6
64+6
96+16
128+14
M4A5-96
M4A5-128
M4A5-192
M4A5-256
M4A3-32
32+2
32+2
32+2
M4A3-64
32+2
32+2
32+2
64+6
48+8
64+6
64+6
64+6
96+16
96+16
128+14, 160
128+14, 192
128+14
160
192
192
256
160
192
M4A3-96
M4A3-128
M4A3-192
M4A3-256
M4A3-384
M4A3-512
4
ispMACH 4A Family
FUNCTIONAL DESCRIPTION
The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized PAL
®
blocks interconnected by a central switch matrix. The central switch matrix allows communication between
PAL blocks and routes inputs to the PAL blocks. Together, the PAL blocks and central switch matrix allow
the logic designer to create large designs in a single device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes. In the
ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms through the logic
allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In
addition, more input routing options are provided by the input switch matrix. These resources provide the
flexibility needed to fit designs efficiently.
PAL Block
4
Clock
Generator
Clock/Input
Pins
Note 3
Note 2
Central Switch Matrix
Logic
Array
Input
Switch
Matrix
Logic 16
Output/
Allocator
Buried
with XOR
Macrocells
16
16
8
Note 1
Dedicated
Input Pins
16
PAL Block
PAL Block
I/O Cells
33/
34/
36
Output Switch Matrix
I/O
Pins
I/O
Pins
I/O
Pins
17466G-001
Figure 1. ispMACH 4A Block Diagram and PAL Block Structure
Notes:
1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4A(3,5)-32/32.
3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch
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