Preliminary Information
4kbit EEPROM
X40430/X40431
DESCRIPTION
The X40430/31 combines power-on reset control,
watchdog timer, supply voltage supervision, secondary
and third voltage supervision, manual reset, and Block
Lock
™
protect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
CC
activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low V
CC
detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
V
CC
falls below the minimum V
TRIP1
point. RESET/
RESET is active until V
CC
returns to proper operating
level and stabilizes. A second and third voltage monitor
circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Xicor’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V/1.7V, 4.4V/2.6V/1.7V,
2.9V/1.7V/2.4V)
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V
CC
= 1V
—Monitor three voltages or detect power fail
• Fault detection register
• Selectable power on reset timeout
• Selectable watchdog timer interval
• Debounced manual reset input
• Low power CMOS
—30µA typical standby current, watchdog on
—10µA typical standby current, watchdog off
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, 1/4, 1/2, all of EEPROM
• 400kHz I
2
C interface
• 2.4V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
BLOCK DIAGRAM
V3MON
V3 Monitor
Logic
V2MON
+
V
TRIP3
-
+
V
TRIP2
-
V3FAIL
V2 Monitor
Logic
V2FAIL
SDA
WP
Data
Register
Command
Decode Test
& Control
Logic
Fault Detection
Register
Status
Register
EEPROM
Array
Watchdog
and
Reset Logic
WDO
MR
SCL
V
CC
(V1MON)
V
CC
Monitor
Logic
+
V
TRIP1
-
Power on,
Manual Reset
Low Voltage
Reset
Generation
RESET
X40430
RESET
X40431
LOWLINE
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X40430/X40431 – Preliminary Information
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
PIN CONFIGURATION
X40430
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
MR
RESET
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
WDO
V3FAIL
V3MON
WP
SCL
SDA
V2FAIL
V2MON
LOWLINE
NC
MR
RESET
V
SS
X40431
14-Pin SOIC, TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
WDO
V3FAIL
V3MON
WP
SCL
SDA
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as x 8. The device features
a 2-wire interface and software protocol allowing opera-
tion on an I
2
C bus.
The device utilizes Xicor’s proprietary Direct Write
™
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN DESCRIPTION
Pin
1
2
Name
V2FAIL
V2MON
Function
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and
goes HIGH when V2MON exceeds V
TRIP2
. There is no power up reset delay circuitry on this pin.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or
V
CC
when not used.
Early Low V
CC
Detect.
This CMOS output signal goes LOW when
V
CC
< V
TRIP1
and goes high
when
V
CC
> V
TRIP1
.
No connect.
Manual Reset Input.
Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t
PURST
thereafter.
RESET Output.
(X40431) This open drain pin is an active LOW output which goes LOW whenever
V
CC
falls below V
TRIP
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power up. It will also stay active until manual reset is released
and for t
PURST
thereafter.
RESET Output.
(X40430) This pin is an active HIGH CMOS output which goes HIGH whenever
V
CC
falls below V
TRIP
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power up. It will also stay active until manual reset is released
and for t
PURST
thereafter.
Ground
3
4
5
6
LOWLINE
NC
MR
RESET/
RESET
7
V
SS
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X40430/X40431 – Preliminary Information
PIN DESCRIPTION
(Continued)
Pin
8
Name
SDA
Function
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH prevents writes to any location in the device (including all the registers).
It has an internal pull down resistor.
V3 Voltage Monitor Input.
When the V3MON input is less than the V
TRIP3
voltage, V3FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a third power supply with no external components. Connect V3MON to V
SS
or
V
CC
when
not used.
V3 Voltage Fail Output.
This open drain output goes LOW when V3MON is less than V
TRIP3
and
goes HIGH when V3MON exceeds V
TRIP3
. There is no power up reset delay circuitry on this pin.
WDO Output.
WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
Supply Voltage
9
10
11
SCL
WP
V3MON
12
13
14
V3FAIL
WDO
V
CC
PRINCIPLES OF OPERATION
Power On Reset
Applying power to the X40430/31 activates a Power
On Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
CC
exceeds the device V
TRIP1
threshold value
for t
PURST
(selectable) the circuit releases the RESET
(X40431) and RESET (X40430) pin allowing the system
to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
X40430
System
Reset
RESET
MR
Manual
Reset
V
CC
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for t
PURST
there-
after.
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Characteristics subject to change without notice.
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X40430/X40431 – Preliminary Information
Low Voltage V
CC
(V1 Monitoring)
During operation, the X40430 monitors the V
CC
level
and asserts RESET if supply voltage falls below a pre-
set minimum V
TRIP1
. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
remains active until V
CC
returns and exceeds V
TRIP1
for
t
PURST
.
Low Voltage V2 Monitoring
The X40430 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V
TRIP2
. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the V2MON drops below 1V (V2MON falling). It
also remains active until V2MON returns and exceeds
V
TRIP2
by 0.2V.
Low Voltage V3 Monitoring
The X40430 also monitors a third voltage level and
asserts V3FAIL if the voltage falls below a preset mini-
mum V
TRIP3
. The V3FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V3FAIL signal remains active
until the V3MON drops below 1V (V3MON falling). It
also remains active until V3MON returns and exceeds
V
TRIP3
by 0.2V.
Early Low V
CC
Detection (LOWLINE)
This CMOS output goes LOW earlier than RESET/
RESET whenever V
CC
falls below the V
TRIP1
voltage
and returns high when V
CC
exceeds the V
TRIP1
volt-
age. There is no power up delay circuitry (t
PURST
) on
this pin.
Figure 2. Two Uses of Multiple Voltage Monitoring
V2MON
X40430
Unreg.
Supply
R
R
5V
Reg
V
CC
RESET
V2MON
V2FAIL
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
V2MON
V
CC
V3MON
X40431
Unreg.
Supply
5V
Reg
4V
Reg
3V
Reg
V
CC
RESET
V2MON
V2FAIL
V3MON
V3FAIL
System
Reset
Notice:
No external components required to monitor three voltages.
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Characteristics subject to change without notice.
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X40430/X40431 – Preliminary Information
Figure 3. V
TRIPX
Set/Reset Conditions
V
TRIPX
(X = 1, 2, 3)
V
CC
/V2MON/V3MON
V
P
WDO
SCL
0
7
0
7
0
7
SDA
A0h
00h
t
WC
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre-
vent a WDO signal going active. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits by writing to the X40430/
31 control register (also refer to page 20).
Figure 4. Watchdog Restart
.6µs
SCL
1.3µs
precision is needed in the threshold value, the X40430
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
Setting a V
TRIPx
Voltage (x=1, 2, 3)
There are two procedures used to set the threshold
voltages (V
TRIPx
), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present V
TRIPx
is 2.9 V and the new
V
TRIPx
is 3.2 V, the new voltage can be stored directly
into the V
TRIPx
cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the V
TRIPx
voltage before setting the new value.
Setting a Higher V
TRIPx
Voltage (x=1, 2, 3)
To set a V
TRIPx
threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired V
TRIPx
threshold voltage to the corre-
sponding input pin (Vcc(V1MON), V2MON or V3MON).
The Vcc(V1MON), V2MON and V3MON must be tied
together during this sequence. Then, a programming
voltage (Vp) must be applied to the WDO pin before a
START condition is set up on SDA. Next, issue on the
SDA pin the Slave Address A0h, followed by the Byte
Address 01h for V
TRIP1
, 09h for V
TRIP2
, and 0Dh for
V
TRIP3
, and a 00h Data Byte in order to program
V
TRIPx
. The STOP bit following a valid write operation
initiates the programming sequence. Pin WDO must
then be brought LOW to complete the operation
SDA
Timer Start
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE
The X40430 is shipped with standard V1, V2 and V3
threshold (V
TRIP1,
V
TRIP2,
V
TRIP3
) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
REV 1.2.3 11/28/00
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Characteristics subject to change without notice.
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