Si5344H, Si5342H Family Revision C and D
Reference Manual
High-Frequency, Ultra-Low Jitter Attenuator Clock with Digitally
Controlled Oscillator
This Family Reference Manual is intended to provide system, PCB design, signal integri-
ty, and software engineers the necessary technical information to successfully use the
Si5344H/42H devices in end applications. The official device specifications can be found
in the Si5344H/42H data sheets.
Related Documents:
• Si5344H/42H Data Sheet
• Si5344H-EVB User Guide
KEY FEATURES
• Status monitoring (LOS, OOF, LOL)
• Hitless input clock switching: automatic or
manual
• Automatic free-run and holdover modes
• Glitchless on the fly output frequency
changes
• Locks to gapped clock inputs
• DCO mode: as low as 0.001 ppb steps.
• Core voltage
• V
DD
: 1.8 V ±5%
• V
DDA
: 3.3 V ±5%
• Independent output supply pins: 3.3 V, 2.5
V, or 1.8 V
• Serial interface: I
2
C or SPI
• In-circuit programmable with non-volatile
OTP memory
• ClockBuilder ProTM software simplifies
device configuratio
• Si5342H: 2 input, 2 output, QFN44
• Si5344H, 2 input, 4 output, QFN44
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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Rev. 1.1
Table of Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Workflow Expectations with ClockBuilder Pro
™
and the Register Map .
1.2 Family Product Comparison .
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1.3 Available Software Tools and Support .
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. 5
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2. DSPLL and MultiSynth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Dividers .
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. 8
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. 9
2.2 DSPLL Loop Bandwidth
2.2.1 Fastlock Feature .
3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Reset and Initialization .
3.2 Dynamic PLL Changes .
3.2.1 Revision C and D.
3.3 NVM Programming .
3.4 Free Run Mode .
3.5 Acquisition Mode .
3.6 Locked Mode .
3.7 Holdover Mode
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.11
.12
.12
.13
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.14
4. Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Inputs (IN0, IN1) . . . . . .
4.1.1 Manual Input Switching. .
4.1.2 Automatic Input Selection .
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16
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.20
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.23
.25
.27
4.2 Types of Inputs . . . . . . . . . .
4.2.1 Unused Inputs. . . . . . . . .
4.2.2 Hitless Input Switching . . . . . .
4.2.3 Glitchless Input Switching . . . . .
4.2.4 Synchronizing to Gapped Input Clocks
4.3 Fault Monitoring . . . . . . . . . . .
4.3.1 Input Loss of Signal (LOS) Fault Detection
4.3.2 Out of Frequency (OOF) Fault Detection .
4.3.3 Loss of Lock Fault Monitoring . . . .
4.4 Interrupt Configuration .
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5. Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1 Output Crosspoint Switch .
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.28
.29
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.31
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5.2 Performance Guidelines for Outputs .
5.3 Output Signal Format . . . . . . . . . . . . . . . .
5.3.1 Differential Output Terminations . . . . . . . . . . .
5.3.2 Differential Output Swing Modes . . . . . . . . . .
5.3.3 Programmable Common Mode Voltage for Differential Outputs
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Rev. 1.1 | 2
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
LVCMOS Output Terminations . . . . . . . . . .
LVCMOS Output Impedance and Drive Strength Selection.
LVCMOS Output Signal Swing . . . . . . . . . .
LVCMOS Output Polarity . . . . . . . . . . . .
Output Driver Settings for LVPECL, LVDS, HCSL, and CML
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.32
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5.4 Output Enable/Disable . . . . . . . .
5.4.1 Output Driver State When Disabled .
5.4.2 Synchronous Output Disable Feature .
5.5 Output Skew Control (t0–t3) .
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6. Digitally-Controlled Oscillator (DCO) Mode
6.1 DCO Register Writes . . .
6.1.1 Other DCO Step Sizes .
6.2 DCO Register Descriptions .
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.38
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7. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 I
2
C Interface .
7.2 SPI Interface .
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40
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.43
8. Field Programming
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. . . . . . . . . . . . . . . . . . . . . . . . . 46
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.46
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9. XAXB External References
9.1 Performance of External References .
9.2 Recommended Crystals and External Oscillators .
9.3 Register Settings to Control External XTAL Reference . . . .
9.3.1 XAXB_FREQ_OFFSET Frequency Offset Register . . .
9.3.2 XAXB_EXTCLK_EN Reference Clock Selection Register .
9.3.3 PXAXB Pre-scale Divide Ratio for Reference Clock Register
10. Crystal and Device Circuit Layout Recommendations
10.1 44-Pin QFN Si5344H/42 Layout Recommendations.
10.1.1 Si5342H/44 Applications without a Crystal . .
10.1.2 Si5342H/44 Crystal Guidelines. . . . . .
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.49
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11. Power Management
. . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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.53
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11.1 Power Management Features .
11.3 Power Supply Sequencing .
11.4 Grounding Vias .
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11.2 Power Supply Recommendations .
12. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12.1 Base vs. Factory Preprogrammed Devices . . . . . .
12.1.1 “Base” Devices (a.k.a. “Blank” Devices). . . . .
12.1.2 “Factory Preprogrammed” (Custom OPN) Devices .
12.2 Register Map Overview and Default Settings Values
12.3 Si5344H Register Definitions . .
12.3.1 Page 0 Registers Si5344H .
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| Building a more connected world.
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.54
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Rev. 1.1 | 3
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.3.7
12.3.8
Page 1 Registers Si5344H
Page 2 Registers Si5344H
Page 3 Registers Si5344H
Page 5 Registers Si5344H
Page 9 Registers Si5344H
Page A Registers Si5344H
Page B Registers Si5344H
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12.4 Si5342H Register Definitions .
12.4.1 Page 0 Registers Si5342H
12.4.2 Page 1 Registers Si5342H
12.4.3 Page 2 Registers Si5342H
12.4.4 Page 3 Registers Si5342H
12.4.5 Page 5 Registers Si5342H
12.4.6 Page 9 Registers Si5342H
12.4.7 Page A Registers Si5342H
12.4.8 Page B Registers Si5342H
.83
.83
.94
.97
. . . . . . . . . . . . . . . . . . . . . . 100
. . . . . . . . . . . . . . . . . . . . . . 103
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. . . . . . . . . . . . . . . . . . . . . . 107
. . . . . . . . . . . . . . . . . . . . . . 108
13. Appendix A—Setting the Differential Output Driver to Non-Standard Amplitudes
14. Document Change List
14.1 Revision 0.9 .
14.2 Revision 1.0 .
14.3 Revision 1.1 .
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. 110
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silabs.com
| Building a more connected world.
Rev. 1.1 | 4
Si5344H, Si5342H Family Revision C and D Reference Manual
Overview
1. Overview
The Si5344H/42H jitter attenuating clock multipliers combine 4
th
generation DSPLL and MultiSynth
™
technologies to enable any-fre-
quency clock generation for applications that require the highest level of jitter performance. These devices are programmable via a seri-
al interface with in-circuit programmable non-volatile memory (NVM) ensuring power up with a known frequency configuration. Free-
run, synchronous, and holdover modes of operation are supported offering both automatic and manual input clock switching. The loop
filter is fully integrated on-chip eliminating the risk of potential noise coupling associated with discrete solutions. Further, the jitter at-
tenuation bandwidth is digitally programmable providing jitter performance optimization at the application level.
These devices are capable of generating any combination of output frequency from any input frequency within the specified input and
output range.
1.1 Workflow Expectations with ClockBuilder Pro
™
and the Register Map
This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details
on how to implement them. It is important to understand that the intent is for customers to use the
ClockBuilder Pro software
to provide
the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a valid
frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other oper-
ating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this document.
Refer to Applications Notes and
Knowledge Base
article links within the ClockBuilder Pro GUI for information on how to implement the
most common, real-time frequency plan changes.
The primary purpose of the software is that it saves having to understand all the complexities of the device. The software abstracts the
details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for
the end application. The software walks the user through each step, with explanations about each configuration step in the process to
explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final
configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to order a
factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing the set-
tings in the register map described in this document.
1.2 Family Product Comparison
The table below lists a comparison of the different family members.
Table 1.1. Product Selection Guide
Part Number
Si5342H
Si5344H
Number of Inputs
2
2
Number of MultiSynths
2
4
Number of Outputs
2
4
Package Type
44-QFN
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