Product Brief
April 2003
MARS1G2 T-LT (TSOT021G2) SONET/SDH
155/622 Mbits/s Overhead and Path Processor
Features
s
One of the next generation system on a chip
devices of Agere Systems’ multiapplication & rate
solutions
MARS
TM
family of framers.
Transmission convergence and SONET/SDH ter-
minal/ADM functionality for linear and ring net-
works.
Versatile IC supports 155/622 Mbits/s SONET/
SDH overhead and path processor solutions.
Low-power 1.6/3.3 V operation.
s
s
s
— T1.105: SONET-Basic Description including
Multiplex Structure, Rates, and Formats.
— T1.105.02 SONET-Payload Mappings.
— T1.105.03 SONET-Jitter at Network Interfaces.
— T1.105.06 SONET Physical Layer Specifica-
tions.
— T1.105.07 SONET-Sub-STS-1 Interface Rates
and Formats Specification.
— ITU-T I.432: B-ISDN User-Network Interface-
Physical Layer Specification.
— IETF RFC 2615: PPP over SONET/SDH.
— IETF RFC 1661: The Point-to-Point Protocol
(PPP).
— IETF RFC 1662: PPP in HDLC-like Framing.
SONET/SDH Interface
s
Interfaces
s
Termination of quad STS-3/STM-1 or dual STS-12/
STM-4.
Supports overhead processing for transport and
path overhead bytes.
Optional insertion and extraction of overhead bytes
via serial overhead interface.
STS pointer processing to align the receive frame
to the system frame.
STS-1 granularity cross connect between receive,
mate, STM, and data payloads.
Support for 1 + 1 and 1:1 linear networks; UPSR
and BLSR ring networks.
Full path termination and SPE extraction/insertion.
SONET/SDH compliant condition and alarm
reporting.
Handles all concatenation levels of STS-3c to
STS-24c (in multiples of 3: e.g., 3c, 6c, 9c, etc.).
Built-in diagnostic loopback modes.
Compliant with the following
Telcordia Technolo-
gies
®
,
ANSI
®
, and ITU standards:
— GR-253 CORE: SONET Transport Systems:
Common Generic Criteria.
— ITU-T G.707: Network Node Interface for the
Synchronous Digital Hierarchy.
— ITU-T G.803: Architecture of Transport Net-
works Based on the Synchronous Digital Hierar-
chy.
Built-in redundant STS/STM backplane interface
using 622 MHz LVDS technology.
Mate-to-mate backplane interface using 622 MHz
LVDS technology for 1 + 1, 1:1, BLSR, and UPSR
network support.
Optional 78 MHz bus (32-bit) for STS/STM inter-
face.
IEEE
®
1149.1 port with BIST, scan, and boundry
scan.
s
s
s
s
s
s
s
s
Microprocessor Interface
s
s
s
s
s
s
Up to 66 MHz synchronous.
16-bit address and 16-bit data interface.
Synchronous or asynchronous modes available.
Configurable to operate with most commercial
microprocessors.
s
s
s
MARS1G2 T-LT (TSOT021G2) SONET/SDH
155/622 Mbits/s Overhead and Path Processor
Product Brief
April 2003
Description
The MARS1G2 T-LT SONET/SDH overhead and path processor provides a versatile solution for quad OC-3 and
dual OC-12, linear and ring datacom/telecom applications. Constructed using COM2 CMOS modular process, this
device incorporates integrated SONET/SDH section/line/path termination, pointer processing, and cross connect
blocks.
Communication with the MARS1G2 T-LT device is accomplished through a generic microprocessor interface. The
device supports separate address and data buses.
With this device, support for different types of applications for OC-3/OC-12 data equipment is possible, enabling
dramatic system cost reduction and the ease of development of extremely competitive solutions.
The interface rates supported are dual STS-12/STM-4 and quad STS-3/STM-1. The concatenation levels sup-
ported by this device are STS-1, STS-3c, STS-6c, STS-9c, STS-12c, STS-15c, . . . , STS-21c, and STS-24c.
MATE
INTERFACE
LINE
INTERFACE
SWITCHING
TSI
PATH
SWITCH
OVERHEAD
PROCESSOR
INSERT
INTERFACE BLOCK
3
STM INTERFACE*
3
DUAL STM
BACKPLANE
INTERFACE
DUAL
STM-4/STS-12
OR QUAD
STM-1/STS-3
STMLSI
78 MHz
LINE
SWITCH
POINTER
PROCESSOR
TXCLK
TRANSPORT
OVERHEAD
TERMINATION
DUAL
STM-4/STS-12
OR QUAD
STM-1/STS-3
PT
CONNECTION
MEMORY
(PTR
INTER)
OVERHEAD
PROCESSOR
MONITOR
CONTROL
MISCELLANEOUS
TXTOAC RXTOAC
TOAC INTERFACE
MPU INTERFACE
GPIO/STMDCC
Note: PT = path terminator.
* An STM low-speed interface (STMLSI) is available.
Figure 1. MARS1G2 T-LT Block Diagram
2
Agere Systems Inc.
Telcordia Technologies
is a trademark of Telcordia Technologies, Inc.
ANSI
is a registered trademark of American National Standards Institute, Inc.
IEEE
is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
docmaster@agere.com
N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138
1-800-372-2447,
FAX 610-712-4106 (In CANADA:
1-800-553-2448,
FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000,
FAX (852) 3129-2020
CHINA:
(86) 21-5047-1212
(Shanghai),
(86) 755-25881122
(Shenzhen)
JAPAN:
(81) 3-5421-1600
(Tokyo), KOREA:
(82) 2-767-1850
(Seoul), SINGAPORE:
(65) 6778-8833,
TAIWAN:
(886) 2-2725-5858
(Taipei)
EUROPE:
Tel. (44) 1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere,
Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.
MARS
is a trademark of Agere Systems Inc.
Copyright © 2003 Agere Systems Inc.
All Rights Reserved
April 2003
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