Data Sheet
August 18, 2004
MARS
®
2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Features
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One of the next-generation, system-on-a-chip
devices of Agere Systems’ multiservice access &
rate solutions
MARS
TM
family of framers.
Transmission convergence and SONET/SDH ter-
minal functionality for linear networks.
Versatile IC supports 155/622/2488 Mbits/s
SONET/SDH interface solutions for packet over
SONET (POS), packet over fiber (POF), or asyn-
chronous transfer mode (ATM) applications.
Low-power 1.6 V/3.3 V operation.
— IETF RFC 2615: PPP over SONET/SDH.
— IETF RFC 1661: The Point-to-Point Protocol
(PPP).
— IETF RFC 1662: PPP in HDLC-like Framing.
Data Processing
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SONET/SDH Interface
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Termination of quad STS-3/STM-1,
quad STS-12/STM-4, or single STS-48/STM-16.
Supports overhead processing for transport and
path overhead bytes.
Optional insertion and extraction of overhead bytes
via serial overhead interface.
STS pointer processing to align the receive frame
to the system frame.
Support for 1 + 1 and 1:1 linear networks.
Full path termination and SPE extraction/insertion.
SONET/SDH compliant condition and alarm
reporting.
Handles all concatenation levels of STS-3c to
STS-48c (in multiples of 3: e.g., 3c, 6c, 9c, etc.).
Built-in diagnostic loopback modes.
Compliant with the following
Telcordia Technolo-
gies
®
,
ANSI
®
, and ITU standards:
— GR-253 CORE: SONET Transport Systems:
Common Generic Criteria.
— ITU-T G.707: Network Node Interface for the
Synchronous Digital Hierarchy.
— ITU-T G.803: Architecture of Transport Net-
works Based on the Synchronous Digital Hierar-
chy.
— T1.105: SONET-Basic Description including
Multiplex Structure, Rates, and Formats.
— T1.105.02 SONET-Payload Mappings.
— T1.105.03 SONET-Jitter at Network Interfaces.
— T1.105.06 SONET Physical Layer Specifica-
tions.
— T1.105.07 SONET-Sub-STS-1 Interface Rates
and Formats Specification.
— ITU-T I.432: B-ISDN User-Network Interface-
Physical Layer Specification.
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Provisionable data engine supports payload inser-
tion/extraction for PPP, ATM, or HDLC streams.
Extraction and insertion of DS3 frames containing
HDLC or ATM data streams for up to 16 channels.
Integrated UTOPIA Level 2 and Level 3 compatible
physical layer interface for packets or ATM cells.
Provides/supports internal E3 mapping.
Supports DS3/PLCP and clear channel DS3 map-
ping.
Insertion and extraction of up to 16 separate data
channels.
Direct cell/packet over fiber interface device.
Compliant with ATM forum, ITU standards, and
IETF standards.
Supports generic framing procedure (GFP) proto-
col.
Interfaces
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Enhanced UTOPIA interface for cell and packet
transfer.
IEEE
®
1149.1 port with BIST, scan, and boundry
scan.
Microprocessor Interface
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Up to 66 MHz synchronous.
16-bit address and 16-bit data interface.
Synchronous or asynchronous modes available.
Configurable to operate with most commercial
microprocessors.
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Table of Contents
Contents
Page
Features ................................................................................................................................................................... 1
SONET/SDH Interface ....................................................................................................................................... 1
Data Processing................................................................................................................................................. 1
Interfaces ........................................................................................................................................................... 1
Microprocessor Interface ................................................................................................................................... 1
Description.............................................................................................................................................................. 27
Generic Framing Procedure (GFP) .................................................................................................................. 28
Target Applications Supported ............................................................................................................................... 29
MARS2G5 P-Pro (600-Pin LBGA and 792-Pin PBGA) .................................................................................... 29
MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) ........................................................................................... 30
MARS622 P-Pro (TDAT12622) (792-Pin PBGA) ............................................................................................. 31
Overview................................................................................................................................................................. 32
Clocking ........................................................................................................................................................... 34
MARS2G5 P-Pro (792-Pin PBGA) Low-Speed Devices Available......................................................................... 36
MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) ........................................................................................... 36
MARS622 P-Pro (TDAT12622) (792-Pin PBGA) ............................................................................................. 36
MARS2G5 P-Pro Device Product Line Table Summaries...................................................................................... 37
Pin Information ....................................................................................................................................................... 38
792-Pin PBGA Pin Assignments ...................................................................................................................... 38
600-Pin LBGA Pin Assignments ...................................................................................................................... 87
Pin Descriptions...................................................................................................................................................... 97
Microprocessor (MPU) Interface........................................................................................................................... 123
Device Address Space Assignments ............................................................................................................. 123
Microprocessor Interface Modes.................................................................................................................... 124
Microprocessor Interface Timing.................................................................................................................... 125
Necessary Register Provisioning Sequence and Clocks ............................................................................... 133
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers....................................................... 134
Performance Monitor (PM) Reset .................................................................................................................. 158
General-Purpose Input/Output Interface ........................................................................................................ 160
Interrupts ........................................................................................................................................................ 162
Loopback Operation....................................................................................................................................... 163
MPU Register Descriptions ............................................................................................................................ 164
MPU Register Map......................................................................................................................................... 173
Functional Description .......................................................................................................................................... 175
Line Interface........................................................................................................................................................ 176
LVPECL I/O Termination and Load Specifications ........................................................................................ 178
Line Interface I/O Timing................................................................................................................................ 180
Transport Overhead Processor (TOHP-48) Block................................................................................................ 184
Introduction .................................................................................................................................................... 184
TOHP-48 Functional Block Diagram .............................................................................................................. 184
Enhancements ............................................................................................................................................... 186
APSMON and K2MON Processing (Including K1K2 Validation and Pass Through) ..................................... 186
TOHP-48 Receive Direction........................................................................................................................... 187
Transmit Direction (to SONET/SDH line) ....................................................................................................... 197
Receive/Transmit TOHP-48 Interface ............................................................................................................ 204
TOHP-48 Register Descriptions..................................................................................................................... 208
TOHP-48 Register Map ................................................................................................................................. 237
Pointer Processor (PP)......................................................................................................................................... 247
Introduction .................................................................................................................................................... 247
Detailed Description ....................................................................................................................................... 250
PP Register Map Overview ............................................................................................................................ 257
PP Register Descriptions ............................................................................................................................... 258
2
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Table of Contents
(continued)
Contents
Page
PP Register Map ............................................................................................................................................ 317
Path Terminator (PT)............................................................................................................................................ 345
Introduction .................................................................................................................................................... 345
SPE Mapper................................................................................................................................................... 346
Supported SPE Formats ................................................................................................................................ 349
SPE Mapper Architecture............................................................................................................................... 352
Transpose Block ............................................................................................................................................ 356
PT Register Descriptions ............................................................................................................................... 357
PT Register Map (Entire PT Except RXT Block)............................................................................................ 385
STS Receive Terminator (RXT) Block.................................................................................................................. 391
Introduction .................................................................................................................................................... 391
Receive Timing Functions.............................................................................................................................. 393
Pointer Interpreter Functions.......................................................................................................................... 394
Concatenation ................................................................................................................................................ 398
RXT Register Descriptions............................................................................................................................. 414
RXT Register Map.......................................................................................................................................... 460
DS3/E3 Block ....................................................................................................................................................... 486
DS3 Functional Description............................................................................................................................ 486
DS3 Transmit Direction .................................................................................................................................. 494
FIFO Block ..................................................................................................................................................... 494
DS3 PLCP Frame/Data Insert........................................................................................................................ 495
DS3 Frame Generate/OH Bit Inserter ............................................................................................................ 497
Transparent Payload Mode (Used in Conjunction with DS3 Mapping) .......................................................... 498
E3 Functional Description .............................................................................................................................. 499
DS3 Register Descriptions ............................................................................................................................. 518
E3 Register Descriptions................................................................................................................................ 550
DS3 Register Map.......................................................................................................................................... 582
E3 Register Map ............................................................................................................................................ 595
Appendix: DS3 to STS-1 Mapping ................................................................................................................. 609
Receive Sequencer (RXS) Block.......................................................................................................................... 611
Introduction .................................................................................................................................................... 611
RXS PRBS Monitor ........................................................................................................................................ 612
RXS Register Descriptions............................................................................................................................. 613
RXS Register Maps........................................................................................................................................ 618
Data Engine Block ................................................................................................................................................ 623
Data Engine Block—Subblocks ..................................................................................................................... 623
Data Engine Block—ATM Framer/Frame Inserter Subblock................................................................................ 624
Overview ........................................................................................................................................................ 624
Capabilities..................................................................................................................................................... 624
Architecture .................................................................................................................................................... 626
Data Engine Block—HDLC Framer and Escaper Subblock ................................................................................. 627
Introduction .................................................................................................................................................... 627
Features ......................................................................................................................................................... 627
Byte-Synchronous Mode................................................................................................................................ 628
Examples of Byte-Synchronous Mode Escaper Operation ............................................................................ 629
Examples of Byte-Synchronous Mode Framer Operation.............................................................................. 631
Bit-Synchronous Mode................................................................................................................................... 632
Examples of Bit-Synchronous Mode Framer Operation................................................................................. 634
Examples of Bit-Synchronous Mode Escaper Operation ............................................................................... 635
Data Engine Block—CRC Generator/Checker Subblock ..................................................................................... 636
Overview ........................................................................................................................................................ 636
Agere Systems Inc.
3
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Table of Contents
(continued)
Contents
Page
Receive .......................................................................................................................................................... 636
Transmit ......................................................................................................................................................... 639
Examples of CRC Insertion/Testing ............................................................................................................... 641
Data Engine Block—PPP Detach Subblock ......................................................................................................... 645
PPP Header Detach....................................................................................................................................... 645
Data Engine Block—Data Engine Counter Subblock ........................................................................................... 648
Introduction .................................................................................................................................................... 648
Overview ........................................................................................................................................................ 648
Implementation .............................................................................................................................................. 648
Data Engine Block—Channel Distribution and Allocation Subblock..................................................................... 651
Channel Distribution and Allocation Subblock Description ............................................................................ 651
Operation and Programming of the CDA Maps ............................................................................................. 652
Data Engine Block—GFP General Framing Procedure Subblock........................................................................ 668
Introduction .................................................................................................................................................... 668
Overview ........................................................................................................................................................ 668
GFP Control Messages.................................................................................................................................. 670
GFP Frame Delineation/Frame Insertion ....................................................................................................... 671
GFP Scrambling/Descrambling...................................................................................................................... 673
Packet-Over-Wavelength Mode ..................................................................................................................... 676
Data Engine Block Registers................................................................................................................................ 677
DE Register Descriptions ............................................................................................................................... 677
DE Register Map............................................................................................................................................ 703
UTOPIA (UT) Block .............................................................................................................................................. 716
UTOPIA Interface Features ........................................................................................................................... 716
UTOPIA Modes .............................................................................................................................................. 718
32-Bit Mode Configuration (Necessary Configuration for Proper Operation)................................................. 718
UT Receive Path (Ingress)............................................................................................................................. 721
UT Transmit Path (Egress) ............................................................................................................................ 724
Address Modes and Pin Assignments of MPHY Interfaces ........................................................................... 726
UTOPIA Loopbacks ....................................................................................................................................... 729
Basic Modes of Operations ............................................................................................................................ 730
Mixed Modes of Operations ........................................................................................................................... 739
Reference Configurations .............................................................................................................................. 741
UTOPIA Interface Pin Description ................................................................................................................. 742
FIFO Ganging ................................................................................................................................................ 744
Packet Packing .............................................................................................................................................. 744
Default Channel Configuration ....................................................................................................................... 744
UTOPIA Interface Timing ............................................................................................................................... 745
UT Global Registers....................................................................................................................................... 748
UT Per-Interface Registers ............................................................................................................................ 750
UT Register Map ............................................................................................................................................ 764
System Interface................................................................................................................................................... 772
ATM Interfaces............................................................................................................................................... 772
POS Interfaces............................................................................................................................................... 775
Test....................................................................................................................................................................... 778
Scan ............................................................................................................................................................... 778
Boundary Scan .............................................................................................................................................. 778
RAM BIST ...................................................................................................................................................... 778
GFP Payload Area CRC-32 Insertion (Version 2.2 and 2.3 Only) ................................................................. 786
Introduction .................................................................................................................................................... 793
4
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Figures
Figure
Page
Figure 1. MARS2G5 P-Pro Block Diagram ............................................................................................................ 27
Figure 2. GFP Relationship to Transport Payloads ............................................................................................... 28
Figure 3. MARS2G5 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 29
Figure 4. MARS1G2 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 30
Figure 5. MARS622 P-Pro Device Interface Speed/Rate Diagram ....................................................................... 31
Figure 6. MARS2G5 P-Pro External Interfaces ..................................................................................................... 33
Figure 7. Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode ................................................................ 34
Figure 8. Clock Domains in the Packet-Over-Fiber (POF) Mode .......................................................................... 35
Figure 9. PLL Outputs Lock-In Process ............................................................................................................... 122
Figure 10. Microprocessor Interface Synchronous Write Cycle (MPU_MPMODE (Pin D8) = 1) ......................... 125
Figure 11. Microprocessor Interface Synchronous Read Cycle (MPU_MPMODE (Pin D8) = 1) ........................ 127
Figure 12. Microprocessor Interface Asynchronous Write Cycle Description (MPU_MPMODE (Pin D8) = 0) .... 129
Figure 13. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) ................................. 131
Figure 14. PM Reset Signal Generation .............................................................................................................. 159
Figure 15. General Input/Output (GPIO) ............................................................................................................. 161
Figure 16. Interrupt Functionality ......................................................................................................................... 162
Figure 17. Loopback Operation ........................................................................................................................... 163
Figure 18. MARS2G5 P-Pro Block Diagram Indicating the Signal Pins per Block .............................................. 175
Figure 19. Line Interface ...................................................................................................................................... 177
Figure 20. LVPECL Load Connections ................................................................................................................ 179
Figure 21. Receive Line-Side Timing Waveform ................................................................................................. 180
Figure 22. Transmit Line-Side Timing Waveform—OC-48 Contraclocking ......................................................... 181
Figure 23. Transmit Line-Side Timing Waveform—OC-48 Forward Clocking ..................................................... 181
Figure 24. Transmit Line-Side Timing Waveform—Frame Sync ......................................................................... 181
Figure 25. High-Level Block Interconnect ............................................................................................................ 184
Figure 26. TOHP-48 Block Diagram (One Channel) ........................................................................................... 185
Figure 27. Time-Slot Assignments ...................................................................................................................... 194
Figure 28. REI-L (MS-REI) Location .................................................................................................................... 202
Figure 29. RTOH Interface .................................................................................................................................. 205
Figure 30. TTOH Interface ................................................................................................................................... 205
Figure 31. STS-3/STM1, STS-12/STM-4, and STS-48/STM-16 Transmit TOAC Interface Timing ..................... 206
Figure 32. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing .............................................. 206
Figure 33. STS-3/STM-1 Receive TOAC Interface Timing .................................................................................. 207
Figure 34. Signal Degrade and Failure Parameters for BER .............................................................................. 228
Figure 35. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of Pointer Processor ........................ 250
Figure 36. Top Level Block Diagram of the Pointer Processor Block .................................................................. 251
Figure 37. Overview of Pointer Processor Register Map .................................................................................... 257
Figure 38. Path Terminator Block Diagram ......................................................................................................... 345
Figure 39. Block Diagram of SPE Mapper Block ................................................................................................. 346
Figure 40. Direct Mapping into STS SPE ............................................................................................................ 349
Figure 41. STS-Nc SPE ....................................................................................................................................... 349
Figure 42. Asynchronous Mapping of DS3 into STS-1 SPE ................................................................................ 350
Figure 43. Asynchronous Mapping of E3 into STS-1 SPE .................................................................................. 351
Figure 44. STS-48 Frame Structure .................................................................................................................... 352
Figure 45. STS-12 Frame Structure .................................................................................................................... 353
Figure 46. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of STS Receive Terminator ............. 391
Figure 47. STS Receive Terminator (RXT) Functional Block Diagram ............................................................... 392
Figure 48. Interpreter State Machine ................................................................................................................... 394
Figure 49. STS-12 RXT Concatenated Offset Passing ....................................................................................... 398
Figure 50. STS-6 RXT Concatenated Offset Passing ......................................................................................... 398
Figure 51. STS-3 and STS-1 RXT Concatenated Offset Passing ....................................................................... 399
Agere Systems Inc.
5
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