a
FEATURES
On-Chip Latches for Both DACs
+5 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/CMOS Compatible
Latch Free (Protection Schottkys not Required)
APPLICATIONS
Digital Control of:
Gain/Attenuation
Filter Parameters
Stereo Audio Circuits
X-Y Graphics
V
DD
DB0
DATA
INPUTS
DB7
CMOS Dual 8-Bit
Buffered Multiplying DAC
AD7528
FUNCTIONAL BLOCK DIAGRAM
V
REF
A
R
FB
A
INPUT
BUFFER
OUT A
LATCH
DAC A
AGND
DAC A/
DAC B
CS
WR
LATCH
DGND
DAC B
CONTROL
LOGIC
AD7528
R
FB
B
OUT B
V
REF
B
GENERAL DESCRIPTION
ORDERING GUIDE
1
Model
2
The AD7528 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount
packages.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
Data is transferred into either of the two DAC data latches via a
common 8-bit TTL/CMOS compatible input port. Control
input
DAC A/DAC
B determines which DAC is to be loaded.
The AD7528’s load cycle is similar to the write cycle of a ran-
dom access memory and the device is bus compatible with most
8-bit microprocessors, including 6800, 8080, 8085, Z80.
The device operates from a +5 V to +15 V power supply, dis-
sipating only 20 mW of power.
Both DACs offer excellent four quadrant multiplication charac-
teristics with a separate reference input and feedback resistor for
each DAC.
PRODUCT HIGHLIGHTS
Temperature
Ranges
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Relative Gain
Accuracy Error
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
4 LSB
±
2 LSB
±
1 LSB
±
4 LSB
±
2 LSB
±
1 LSB
±
4 LSB
±
2 LSB
±
1 LSB
±
4 LSB
±
2 LSB
±
1 LSB
±
4 LSB
±
2 LSB
±
1 LSB
Package
Options
3
N-20
N-20
N-20
P-20A
P-20A
P-20A
R-20
R-20
R-20
Q-20
Q-20
Q-20
Q-20
Q-20
Q-20
AD7528JN
AD7528KN
AD7528LN
AD7528JP
AD7528KP
AD7528LP
AD7528JR
AD7528KR
AD7528LR
AD7528AQ
AD7528BQ
AD7528CQ
AD7528SQ
AD7528TQ
AD7528UQ
1. DAC-to-DAC matching: since both of the AD7528 DACs are
fabricated at the same time on the same chip, precise match-
ing and tracking between DAC A and DAC B is inherent.
The AD7528’s matched CMOS DACs make a whole new
range of applications circuits possible, particularly in the
audio, graphics and process control areas.
2. Small package size: combining the inputs to the on-chip DAC
latches into a common data bus and adding a
DAC A/DAC
B
select line has allowed the AD7528 to be packaged in either a
small 20-lead DIP, SOIC or PLCC.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
NOTES
1
Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts
will be marked with cerdip designator “Q.”
2
Processing to MIL-STD-883C, Class B is available. To order, add suffix “/883B” to
part number. For further information, see Analog Devices’ 1990 Military Products
Databook.
3
N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
AD7528–SPECIFICATIONS
(V
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
2
REF
A
= V
REF
B = +10 V; OUT A = OUT B = O V unless otherwise noted)
V
DD
= +15 V
T
A
= +25°C T
MIN
, T
MAX
8
±
1
±
1/2
±
1/2
±
1
±
4
±
2
±
1
±
0.0035
±
50
±
50
8
15
±
1
8
±
1
±
1/2
±
1/2
±
1
±
5
±
3
±
1
±
0.0035
±
200
±
200
8
15
±
1
Units
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Test Conditions/Comments
V
DD
= +5 V
Version
All
J, A, S
K, B, T
L, C, U
All
J, A, S
K, B, T
L, C, U
1
T
A
= +25°C
8
±
1
±
1/2
±
1/2
±
1
±
4
±
2
±
1
±
0.007
±
50
±
50
8
15
±
1
T
MIN
, T
MAX
8
±
1
±
1/2
±
1/2
±
1
±
6
±
4
±
3
±
0.007
±
400
±
400
8
15
±
1
This is an Endpoint Linearity Specification
Differential Nonlinearity
Gain Error
All Grades Guaranteed Monotonic Over
Full Operating Temperature Range
Measured Using Internal R
FB
A and R
FB
B
Both DAC Latches Loaded with 11111111
Gain Error is Adjustable Using Circuits
of Figures 4 and 5
Gain Temperature Coefficient
3
∆Gain/∆Temperature
Output Leakage Current
OUT A (Pin 2)
OUT B (Pin 20)
Input Resistance (V
REF
A, V
REF
B)
V
REF
A/V
REF
B Input Resistance
Match
DIGITAL INPUTS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Current
I
IN
Input Capacitance
DB0–DB7
WR, CS, DAC A/DAC
B
SWITCHING CHARACTERISTICS
3
Chip Select to Write Set Up Time
t
CS
Chip Select to Write Hold Time
t
CH
DAC Select to Write Set Up Time
t
AS
DAC Select to Write Hold Time
t
AH
Data Valid to Write Set Up Time
t
DS
Data Valid to Write Hold Time
t
DH
Write Pulsewidth
t
WR
POWER SUPPLY
I
DD
4
All
All
All
All
%/°C max
nA max
nA max
kΩ min
kΩ max
% max
DAC Latches Loaded with 00000000
Input Resistance TC = –300 ppm/°C, Typical
Input Resistance is 11 kΩ
All
All
All
All
All
All
2.4
0.8
±
1
10
15
2.4
0.8
±
10
10
15
13.5
1.5
±
1
10
15
13.5
1.5
±
10
10
15
V min
V max
µA
max
pF max
pF max
See Timing Diagram
V
IN
= 0 or V
DD
All
All
All
All
All
All
All
All
All
90
0
90
0
80
0
90
2
100
100
0
100
0
90
0
100
2
500
60
10
60
10
30
0
60
2
100
80
15
80
15
40
0
80
2
500
ns min
ns min
ns min
ns min
ns min
ns min
ns min
mA max
µA
max
See Figure 3
All Digital Inputs V
IL
or V
IH
All Digital Inputs 0 V or V
DD
AC PERFORMANCE CHARACTERISTICS
Parameter
DC SUPPLY REJECTION (∆GAIN/∆V
DD
)
CURRENT SETTLING TIME
2
5
(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as
Output Amplifiers)
V
DD
= +15 V
Test Conditions/Comments
To 1/2 LSB. OUT A/OUT B Load = 100
Ω.
WR
=
CS
= 0 V. DB0–DB7 = 0 V to V
DD
or
V
DD
to 0 V
V
REF
A = V
REF
B = +10 V
OUT A, OUT B Load = 100
Ω
C
EXT
= 13 pF
WR
=
CS
= 0 V DB0–DB7 = 0 V to V
DD
or
V
DD
to 0 V
For Code Transition 00000000 to 11111111
DAC Latches Loaded with 00000000
DAC Latches Loaded with 11111111
0.01
180
0.02
200
% per % max
∆V
DD
=
±
5%
ns max
V
DD
= +5 V
Version
All
All
1
T
A
= +25°C
0.02
350
T
MIN
, T
MAX
T
A
= +25°C T
MIN
, T
MAX
Units
0.04
400
PROPAGATION DELAY (From Digital In-
put to 90% of Final Analog Output Current)
All
220
270
80
100
ns max
DIGITAL-TO-ANALOG GLITCH IMPULSE All
OUTPUT CAPACITANCE
C
OUT
A
C
OUT
B
C
OUT
A
C
OUT
B
AC FEEDTHROUGH
6
V
REF
A to OUT A
V
REF
B to OUT B
All
160
50
50
120
120
–70
–70
50
50
120
120
–65
–65
440
50
50
120
120
–70
–70
50
50
120
120
–65
–65
nV sec typ
pF max
pF max
pF max
pF max
dB max
dB max
All
V
REF
A, V
REF
B = 20 V p-p Sine Wave
@ 100 kHz
–2–
REV. B
AD7528
V
DD
= +5 V
Parameter
CHANNEL-TO-CHANNEL ISOLATION
V
REF
A to OUT B
V
REF
B to OUT A
DIGITAL CROSSTALK
HARMONIC DISTORTlON
All
All
Version
All
1
V
DD
= +15 V
Test Conditions/Comments
Both DAC Latches Loaded with 11111111.
V
REF
A = 20 V p-p Sine Wave @ 100 kHz
V
REF
B = 0 V see Figure 6.
V
REF
A = 20 V p-p Sine Wave @ 100 kHz
V
REF
A = 0 V see Figure 6.
Measured for Code Transition 00000000 to
11111111
V
IN
= 6 V rms @ 1 kHz
T
A
= +25°C
–77
–77
30
–85
T
MIN
, T
MAX
T
A
= +25°C T
MIN
, T
MAX
Units
–77
–77
60
–85
dB typ
dB typ
nV sec typ
dB typ
NOTES
1
Temperature Ranges are J, K, L Versions: –40°C to +85°C
A, B, C Versions: –40°C to +85°C
S, T, U Versions: –55°C to +125°C
2
Specifications applies to both DACs in AD7528.
3
Guaranteed by design but not production tested.
4
Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA.
5
These characteristics are for design guidance only and are not subject to test.
6
Feedthrough can be further reduced by connecting the metal lid on the ceramic package
(suffix D) to DGND.
Specifications subject to change without notice.
AD7528, ideal maximum output is V
REF
– 1 LSB. Gain error of
both DACs is adjustable to zero with external resistance.
Output Capacitance
Capacitance from OUT A or OUT B to AGND.
Digital to Analog Glitch lmpulse
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+ 0.3 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
PIN2
, V
PIN20
to AGND . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
A, V
REF
B to AGND . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
V
RFB
A, V
RFB
B to AGND . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (J, K, L) Grades . . . . . . . . . . . –40°C to +85°C
Industrial (A, B, C) Grades . . . . . . . . . . . . –40°C to +85°C
Extended (S, T, U) Grades . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
CAUTION:
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with V
REF
A,
V
REF
B = AGND.
Propagation Delay
This is a measure of the internal delays of the circuit and is
defined as the time from a digital input change to the analog
output current reaching 90% of its final value.
Channel-to-Channel Isolation
The proportion of input signal from one DAC’s reference input
which appears at the output of the other DAC, expressed as a
ratio in dB.
Digital Crosstalk
The glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Speci-
fied in nV secs.
PIN CONFIGURATIONS
PLCC
OUT A
OUT B
20
1. ESD sensitive device. The digital control inputs are diode
protected; however, permanent damage may occur on uncon-
nected devices subjected to high energy electrostatic fields.
Unused devices must be stored in conductive foam or shunts.
2. Do not insert this device into powered sockets. Remove
power before insertion or removal.
TERMINOLOGY
Relative Accuracy
V
REF
A
4
DGND
5
DAC A/DAC
B
(MSB) DB7
6
7
AGND
R
FB
A
3
2
1
PIN 1
IDENTIFIER
R
FB
B
19
18
17
V
REF
B
V
DD
WR
CS
DB0 (LSB)
AD7528
TOP VIEW
(Not to Scale)
16
15
14
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full scale reading.
Differential Nonlinearity
DB6
8
9
10
11
12
13
DB5
DB4
DB3
DB2
DB1
DIP, SOIC
AGND
1
OUT A
2
R
FB
A
3
V
REF
A
4
DGND
5
DAC A/DAC
B
6
20
OUT B
19
R
FB
B
18
V
REF
B
17
V
DD
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
±
1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error
AD7528
16
WR
TOP VIEW
15
CS
(Not to Scale)
14
DB0 (LSB)
(MSB) DB7
7
DB6
8
DB5
9
DB4
10
13
DB1
12
DB2
11
DB3
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For the
REV. B
–3–
AD7528
INTERFACE LOGIC INFORMATION
DAC Selection:
Both DAC latches share a common 8-bit input port. The con-
trol input
DAC A/DAC
B selects which DAC can accept data
from the input port.
Mode Selection:
Figure 1. An inverted R-2R ladder structure is used, that is, bi-
nary weighted currents are switched between the DAC output
and AGND thus maintaining fixed currents in each ladder leg
independent of switch state.
EQUIVALENT CIRCUIT ANALYSIS
Inputs
CS
and
WR
control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode:
When
CS
and
WR
are both low the selected DAC is in the write
mode. The input data latches of the selected DAC are transpar-
ent and its analog output responds to activity on DB0–DB7.
Hold Mode:
Figure 2 shows an approximate equivalent circuit for one of the
AD7528’s D/A converters, in this case DAC A. A similar
equivalent circuit can be drawn for DAC B. Note that AGND
(Pin 1) is common for both DAC A and DAC B.
The current source I
LEAKAGE
is composed of surface and junc-
tion leakages and, as with most semiconductor devices, approxi-
mately doubles every 10°C. The resistor R
O
as shown in Figure
2 is the equivalent output resistance of the device which varies
with input code (excluding all 0s code) from 0.8 R to 2 R. R is
typically 11 kΩ. C
OUT
is the capacitance due to the N-channel
switches and varies from about 50 pF to 120 pF depending
upon the digital input. g(V
REF
A, N) is the Thevenin equivalent
voltage generator due to the reference input voltage V
REF
A and
the transfer function of the R-2R ladder.
R
R
O
g(V
REF
A, N)
I
LKG
C
OUT
AGND
R
FB
A
OUT A
The selected DAC latch retains the data which was present on
DB0–DB7 just prior to
CS
or
WR
assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
DAC A/DAC
B
L
H
X
X
CS
L
L
H
X
WR
L
L
X
H
DAC A
WRITE
HOLD
HOLD
HOLD
DAC B
HOLD
WRITE
HOLD
HOLD
L = Low State; H = High State; X = Don’t Care.
Figure 2. Equivalent Analog Output Circuit of DAC A
WRITE CYCLE TIMING DIAGRAM
CHIP SELECT
t
CS
t
CH
CIRCUIT INFORMATION–DIGITAL SECTION
V
DD
0
DAC A/DAC
B
t
AS
t
WR
t
AH
V
DD
0
V
DD
0
WRITE
t
DS
DATA IN
(DB0 – DB7)
V
IH
V
IL
t
DH
V
DD
0
The input buffers are simple CMOS inverters designed such
that when the AD7528 is operated with V
DD
= 5 V, the buffer
converts TTL input levels (2.4 V and 0.8 V) into CMOS logic
levels. When V
IN
is in the region of 2.0 volts to 3.5 volts the
input buffers operate in their linear region and pass a quiescent
current, see Figure 3. To minimize power supply currents it is
recommended that the digital input voltages be as close to the
supply rails (V
DD
and DGND) as is practically possible.
The AD7528 may be operated with any supply voltage in the
range 5
≤
V
DD
≤
15 volts. With V
DD
= +15 V the input logic
levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
9
800
I
DD
A (V
DD
= +5V)
700
600
500
400
300
200
100
V
DD
= +5V
V
DD
= +15V
T
A
= +25 C
ALL DIGITAL INPUTS
TIED TOGETHER
8
I
DD
mA (V
DD
= +15V)
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
V
IN
– Volts
9
10
11
12
13
14
DATA IN STABLE
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED
FROM 10% TO 90% OF V
DD
.
V
DD
= +5V,
t
r =
t
f = 20ns;
V
DD
= +15V,
t
r =
t
f = 40ns;
V
IH
+ V
IL
2. TIMING MEASUREMENT REFERENCE LEVEL IS
2
CIRCUIT INFORMATION—D/A SECTION
The AD7528 contains two identical 8-bit multiplying D/A con-
verters, DAC A and DAC B. Each DAC consists of a highly
stable thin film R-2R ladder and eight N-channel current steer-
ing switches. A simplified D/A circuit for DAC A is shown in
R
V
REF
A
2R
S1
2R
S2
2R
S3
2R
S8
2R
R
R
FB
A
OUT A
AGND
DAC A
DATA LATCHES
AND DRIVERS
R
R
Figure 3. Typical Plots of Supply Current, I
DD
vs. Logic
Input Voltage V
IN
, for V
DD
= +5 V and +15 V
Figure 1. Simplified Functional Circuit for DAC A
–4–
REV. B
AD7528
V
IN
A
(± 10V)
R1
1
R2
1
V
DD
DB0
DATA
INPUTS
DB7
INPUT
BUFFER
LATCH
DAC A
R
FB
A
OUT A
AGND
AGND
C1
2
V
OUT
A
Table I. Unipolar Binary Code Table
DAC Latch Contents
MSB
LSB
11111111
10000001
10000000
V
OUT
B
AGND
Analog Output
(DAC A or DAC B)
255
–V
IN
256
129
–V
IN
256
V
128
–V
IN
= −
IN
256
2
127
–V
IN
256
1
–V
IN
256
0
–V
IN
=
0
256
1
(
V
)
256
IN
DAC A/
DAC B
CS
WR
DGND
AD7528
CONTROL
LOGIC
LATCH
DAC B
R4
1
R
FB
B
OUT B
C2
2
01111111
00000001
00000000
Note: 1 LSB =
2
−8
(
V
IN
)
=
R3
1
V
IN
B
(± 10V)
NOTES:
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
2
C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN
USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
( )
Figure 4. Dual DAC Unipolar Binary Operation
(2 Quadrant Multiplication); See Table I
V
IN
A
(± 10V)
R5
20k
R1
1
R2
1
V
DD
DB0
DATA
INPUTS
DB7
INPUT
BUFFER
LATCH
DAC A
R
FB
A
OUT A
AGND
AGND
DAC A/
DAC B
CS
WR
DGND
R6
2
20k
R7
2
10k
C1
3
A1
A2
R11
5k
AGND
V
OUT
A
Table II. Bipolar (Offset Binary) Code Table
DAC Latch Contents Analog Output
MSB
LSB
(DAC A or DAC B)
11111111
10000001
10000000
0
1
–V
IN
128
127
–V
IN
128
128
–V
IN
128
1
(
V
)
128
IN
127
+V
IN
128
AD7528
CONTROL
LOGIC
LATCH
DAC B
R4
1
R
FB
B
OUT B
AGND
R3
1
C2
3
A3
R9
2
10k
R10
2
20k
A4
R12
5k
AGND
V
OUT
B
R8
20k
01111111
00000001
00000000
Note: 1 LSB =
2
−7
(
V
IN
)
=
V
IN
B
(± 10V)
NOTES:
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
ADJUST R1 FOR V
OUT
A = 0V WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR V
OUT
B = 0V WITH CODE 10000000 IN DAC B LATCH.
2
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R6, R7 AND R9, R10.
3
C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED
IF A1/A3 IS A HIGH SPEED AMPLIFIER.
( )
Table III. Recommended Trim Resistor
Values vs. Grade
Figure 5. Dual DAC Bipolar Operation
(4 Quadrant Multiplication); See Table II
Trim
Resistor
R1; R3
R2; R4
J/A/S
1k
330
K/B/T
500
150
L/C/U
200
82
REV. B
–5–
嵌入式系统
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