Si532
P
R E L I M I N A R Y
D
A TA
S
H E E T
D
U A L
F
R E Q U E N C Y
X O ( 1 0 M H
Z T O
1 . 4 GH
Z
)
Features
Available with any-rate output
frequencies from 10 to 945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
Industry standard 7x5 mm package
Available CMOS, LVPECL, LVDS &
CML outputs
3.3, 2.5, and 1.8 V supply options
3x better frequency stability than
SAW based oscillators
3rd generation DSPLL with
superior jitter performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Lead-free/RoHS-compliant
®
Si5602
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Low jitter clock generation
Optical modules
Test and measurement
Ordering Information:
See page 7.
Description
The Si532 dual frequency XO utilizes Silicon Laboratories advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si532 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional XOs where a
different crystal is required for each output frequency, the Si532 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to be optimized for superior
frequency, stability, and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments often found in communication
systems. The Si532 IC based XO is factory configurable for a wide variety of
user specifications including frequency, supply voltage, and output format.
Specific configurations are factory programmed into the Si532 at the time of
shipment, thereby eliminating the long lead times associated with custom
oscillators.
Functional Block Diagram
V
DD
CLK–
CLK+
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL®
Clock
Synthesis
FS
OE
GND
Preliminary Rev. 0.3 12/05
Copyright © 2005 by Silicon Laboratories
Si532
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si532
1. Electrical Specifications
Table 1. Si532 Electrical Specifications
Parameter
Min
Typ
Max
Units
Notes
Frequency
Nominal Frequency
LVDS/CML/LVPECL
CMOS
Initial Accuracy
10
10
–1.5
–20
–50
—
—
—
—
—
—
—
945
160
1.5
+20
+50
±10
Outputs
Symmetry
RMS Jitter for F
OUT
> 500 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
RMS Jitter for F
OUT
of 125 to
500 MHz
12 kHz to 20 MHz
Period Jitter for F
OUT
<160 MHz
Peak-to-Peak
RMS
LVPECL Output Option
mid-level
swing (diff)
swing (single-ended)
LVDS Output Option
mid-level
swing (diff)
MHz
Specified at time of order by P/N.
Also available in bands from
970 to 1134 MHz and 1213 to
1417 MHz.
Measured at +25 °C at time of ship-
ping
Selectable option by P/N. See
Section 4. "Ordering Information" on
page 7.
Frequency drift over projected 15 year
life
ppm
Temperature Stability
Aging
ppm
ppm
45
—
55
%
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (differential)
1.25 V (differential)
V
DD
/2
—
—
0.27
0.30
—
—
ps
F
OUT
> 500 MHz
Differential Modes:
LVPECL/LVDS/CML
125 < F
OUT
< 500 MHz
Differential Modes:
LVPECL/LVDS/CML
Any output
N = 1000 cycles
—
—
—
V
DD
– 1.42
1.1
0.50
0.5
5
1
—
—
—
—
—
—
V
DD
– 1.25
1.9
0.93
ps
ps
V
V
PP
V
PP
50
Ω
to V
DD
– 2.0 V
1.125
0.32
1.2
0.40
1.275
0.50
V
V
PP
R
term
= 100
Ω
(differential)
CML Output Option
mid-level
swing
—
0.70
V
DD
– 0.75
0.95
—
1.20
V
V
PP
Rterm = 100
Ω
(differential)
2
Preliminary Rev. 0.3
Si532
Table 3. Environmental Conditions
Parameter
Operating Temperature
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Conditions/Test Method
–40 to +85 °C
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Table 4. Pinout
Pin
1
2
3
4
5
6
Symbol
FS
OE
GND
CLK+
CLK–
(N/A for CMOS)
V
DD
Function
Frequency Select
Output Enable
Ground
Oscillator Output
Complementary Output
(N/C for CMOS)
Power Suppy Voltage
4
Preliminary Rev. 0.3
FPGA/CPLD
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