电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

552EE622M080BGR

产品描述DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)
文件大小173KB,共8页
制造商SILABS
官网地址http://www.silabs.com
下载文档 全文预览

552EE622M080BGR概述

DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)

文档预览

下载PDF文档
Si552
P
R E L I M I N A R Y
D
A TA
S
H E E T
D
U A L
F
R E Q U E N C Y
VCXO (10 M H
Z T O
1.4 GH
Z
)
Features
Available with any-rate output
frequencies from 10 to 945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
Industry-standard 7x5 mm package
Available CMOS, LVPECL, LVDS &
CML outputs
3x better frequency stability than
SAW-based oscillators
3rd generation DSPLL with
superior jitter performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Lead-free/RoHS-compliant
®
Si5602
Applications
SONET / SDH
xDSL
10 GbE LAN / WAN
Low jitter clock generation
Optical Modules
Test and Measurement
Ordering Information:
See page 7.
Description
The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXO’s where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to be optimized for superior
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments often found in communication
systems. The Si552 IC based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage and output
format. Specific configurations are factory programmed into the Si552 at
time of shipment, thereby eliminating the long lead times associated with
custom oscillators.
Functional Block Diagram
V
DD
CLK- CLK+
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL™
Clock Synthesis
ADC
V
C
FS
GND
Preliminary Rev. 0.2 8/05
Copyright © 2005 by Silicon Laboratories
Si552
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

技术资料推荐更多

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1936  2235  2335  969  2358  39  46  48  20  36 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved