Si5540
P
R E L I M I N A R Y
D
A TA
S
H E E T
SiPHY
™
OC-192/STM-64 T
RANSMITTER
Features
Complete SONET/SDH transmitter for OC-192/STM-64 data rates with integrated
16:1 multiplexer and DSPLL
™
based clock multiplier unit:
Data Rates Supported: OC-192/STM-64,
10GbE, and 10.7 Gbps FEC
Low Power Operation 0.6 W (typ)
Small Footprint: 99-Pin BGA Package
(11 x 11 mm)
OIF SFI-4 Compliant Interface
Output Clock Powerdown
Operates with 155 or 622 MHz
Reference Sources
Optional 3.3 V Supply Pin for
LVTTL Compatible Outputs
Single 1.8 V Supply Operation
Si5364
DSPLL™ Based Clock Multiplier Unit
w/ selectable loop filter bandwidths
Bottom View
Applications
Sonet/SDH/ATM Routers
Add/Drop Multiplexers
Digital Cross Connects
Optical Transceiver Modules
Sonet/SDH Test Equipment
Ordering Information:
See page 17.
Description
The Si5540 is a fully integrated low-power transmitter for high-speed serial
communication systems. It combines high speed clock generation with a 16:1
multiplexer to serialize data for OC-192/STM-64 applications. The Si5540 is based
on Silicon Laboratories’ DSPLL
™
technology which eliminates the external loop
filter components required by traditional clock multiplier units. In addition,
selectable loop filter bandwidths are provided to ensure superior jitter performance
while relaxing the jitter requirements on external clock distribution subsystems.
Support for data streams up to 10.7 Gbps is also provided for applications that
employ forward error correction (FEC).
The Si5540 represents a new standard in low jitter, low power and small size for
10 Gbps serial transmitters. It operates from a single 1.8 V supply over the
industrial temperature range (–40°C to 85°C).
Functional Block Diagram
R EFSEL
R EFC LK
2
R EFRATE
TXC LK16IN
TXLOL
BW SEL
TXC LKD SBL
TXCL KOUT
TXDOU T
2
16:1
MUX
FIFO
2
R eset
Con trol
D SPLL
TM
CMU
2
2
32
÷
16
TXCL K16OU T
TXCL K16IN
TXDIN [15:0]
FIF ORST
B ias
R EXT
RES ET
F IFOER R
TXSQLC H
TX M SBSEL
Preliminary Rev. 0.31 8/01
Copyright © 2001 by Silicon Laboratories
Si5540-DS031
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si 5540
2
Preliminary Rev. 0.31
Si5540
T
A B L E O F
C
O N T E N TS
Section
Page
4
9
9
9
9
10
10
10
11
12
14
17
18
20
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSPLL™ Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Si5540 Pinout: 99-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions: Si5540 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.31
3
Si 5540
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
LVTTL Output Supply Voltage
Si5540 Supply Voltage
Symbol
T
A
V
DD33
V
DD
Test Condition
Min*
–40
1.71
1.71
Typ
25
—
1.8
Max*
85
3.47
1.89
Unit
°C
V
V
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25
°
C unless otherwise stated.
V
SIGNAL +
Differential
V
ICM
, V
OCM
I/Os
SIGNAL –
V
IS
Single Ended Voltage
(SIGNAL +) – (SIGNAL –)
Differential
Voltage Swing
V
ID
,V
OD
(V
ID
= 2V
IS
)
Differential Peak-to-Peak Voltage
t
Figure 1. Differential Voltage Measurement (TXDIN, TXDOUT, TXCLK16IN, TXCLK16OUT)
t
su
TXDOUT,
TXDIN
t
hd
t
CH
TXCLKOUT,
TXCLK16IN
t
CP
Figure 2. Data to Clock Delay
All Differential
IOs
t
F
t
R
80%
20%
Figure 3. Rise/Fall Time Measurement
4
Preliminary Rev. 0.31
Si5540
Table 2. DC Characteristics, V
DD
= 1.8 V
(V
DD
= 1.8 V ±5%, T
A
= –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current
Power Dissipation
Common Mode Output Voltage
(TXDOUT,TXCLKOUT)
Differential Output Voltage Swing
(TXDOUT,TXCLKOUT), Differential pk-pk
LVPECL Input Voltage High (REFCLK)
LVPECL Input Voltage Low (REFCLK)
LVPECL Input Voltage Swing (REFCLK),
Differential pk-pk
LVPECL Input Common Mode (REFCLK)
Input Impedance
(REFCLK, TXDIN, TXCLK16IN)
LVDS Input High Voltage (TXDIN,
TXCLK16IN)
LVDS Input Low Voltage (TXDIN,
TXCLK16IN)
LVDS Input Voltage, Single Ended pk-pk
(TXDIN, TXCLK16IN)
LVDS Input Common Mode Voltage
(TXDIN, TXCLK16IN)
LVDS Output High Voltage
(TXCLK16OUT)
LVDS Output Low Voltage
(TXCLK16OUT)
LVDS Output Voltage, Single Ended pk-pk
(TXCLK16OUT)
LVDS Output Common Mode Voltage
(TXCLK16OUT)
Output Short to GND
(TXCLK16OUT, TXDOUT, TXCLKOUT)
Output Short to V
DD
(TXCLK16OUT, TXDOUT, TXCLKOUT)
LVTTL Input Voltage Low
(TXCLKDSBL, FIFORST, TXSQLCH,
BWSEL, REFRATE, REFSEL, TXMSBSEL,
RESET)
I
DD
P
D
V
OCM
V
OD
V
IH
V
IL
V
ID
V
ICM
R
IN
V
IH
V
IL
V
ISE
V
ICM
V
OH
V
OL
V
OSE
100
Ω
Load
Line-to-Line
100
Ω
Load
Line-to-Line
100
Ω
Load
Line-to-Line, See
Figure 1
Each input to
common mode
See Figure 1
—
—
.8
800
1.975
1.32
250
1.65
42
—
0.0
100
.8
TBD
0.925
250
333
0.6
0.9
1000
2.3
1.6
—
1.95
50
—
—
—
2.0
—
—
400
TBD
TBD
1.0
1200
2.59
1.99
2600
2.30
58
2.4
—
600
2.4
1.475
TBD
550
mA
W
V
mV
(pk-pk)
V
V
mV
(pk-pk)
V
Ω
V
V
mV
(pk-pk)
V
V
V
mV
(pk-pk)
V
mA
µ
A
V
OCM
I
SC–
I
SC+
V
IL2
1.125
—
TBD
—
1.20
25
–100
—
1.275
TBD
—
0.8
V
Preliminary Rev. 0.31
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
