56F802
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F802
Rev. 9
01/2007
freescale.com
56F802 General Description
• Up to 30 MIPS operation at 60MHz core frequency
• Up to 40 MIPS operation at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module with fault input
• Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
• Serial Communications Interface (SCI)
• Two General Purpose Quad Timers with 2 external
outputs
• 8K
×
16-bit words (16KB) Program Flash
• 1K
×
16-bit words (2KB) Program RAM
• 2K
×
16-bit words (4KB) Data Flash
• 1K
×
16-bit words (2KB) Data RAM
• 2K
×
16-bit words (4KB) Boot Flash
• JTAG/OnCE
TM
port for debugging
• On-chip relaxation oscillator
• 4 shared GPIO
• 32-pin LQFP Package
6
PWM Outputs
Fault A0
PWMA
RESET
5
JTAG/
OnCE
Port
VCAPC V
DD
2
2
V
SS
* V
DDA
3
Digital Reg
Analog Reg
V
SSA
2
3
A/D1
A/D2
VREF
ADC
Interrupt
Controller
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
2
Quad Timer D
or GPIO
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
•
PAB
•
•
PDB
•
•
•
•
IPBB
CONTROLS
16
Relaxation
Oscillator
PLL
XDB2
CGDB
XAB1
XAB2
.
•
2
SCI0
or
GPIO
INTERRUPT
CONTROLS
16
COP/
Watchdog
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
16-Bit
56800
Core
Applica-
tion-Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
*
includes TCS pin which is reserved for factory use and is tied to VSS
56F802 Block Diagram
56F802 Technical Data, Rev. 9
Freescale Semiconductor
3
Part 1 Overview
1.1 56F802 Features
1.1.1
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•
•
•
•
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Processing Core
Efficient 16-bit 56800 family controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
•
•
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
On-chip memory including a low-cost, high-volume Flash solution
— 8K
×
16 bit words of Program Flash
— 1K
×
16-bit words of Program RAM
— 2K
×
16-bit words of Data Flash
— 1K
×
16-bit words of Data RAM
— 2K
×
16-bit words of Boot Flash
•
Programmable Boot Flash supports customized boot code and field upgrades of stored code through a
variety of interfaces (JTAG)
1.1.3
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Peripheral Circuits for 56F802
Pulse Width Modulator (PWM) with six PWM outputs with deadtime insertion and fault protection;
supports both center- and edge-aligned modes
Two 12-bit, Analog-to-Digital Converters (ADCs), 1 x 2 channel and 1 x 3 channel, which support two
simultaneous conversions; ADC and PWM modules can be synchronized
Two General Purpose Quad Timers with two external pins (or two GPIO)
Serial Communication Interface (SCI) with two pins (or two GPIO)
Four multiplexed General Purpose I/O (GPIO) pins
56F802 Technical Data, Rev. 9
4
Freescale Semiconductor
56F802 Description
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Computer-Operating Properly (COP) watchdog timer
External interrupts via GPIO
Trimmable on-chip relaxation oscillator
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4
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Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
Integrated power supervisor
1.2 56F802 Description
The 56F802 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and
compact program code, the 56F802 is well-suited for many applications. The 56F802 includes many
peripherals that are especially useful for applications such as motion control, home appliances, encoders,
tachometers, limit switches, power supply and control, engine management, and industrial control for
power, lighting, automation and HVAC.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F802 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F802 also provides and up to 4
General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F802 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
A key application-specific feature of the 56F802 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs
to enhance motor control functionality. Complementary operation permits programmable dead-time
56F802 Technical Data, Rev. 9
Freescale Semiconductor
5
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