PL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
r d
O.T.)
FEATURES
100MHz to 200MHz Fundamental or 3
rd
Overtone Crystal input.
Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier) or 400 – 700MHz
(4x multiplier).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
62 mil
DIE CONFIGURATION
65 mil
OUTSEL0^
OUTSEL1^
SEL0^
SEL1^
VDD
VDD
VDD
VDD
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^
XIN
XOUT
SEL3^
SEL2^
OE
CTRL
NC
26
27
Die ID:
A1010-10A
15
28
14
DESCRIPTION
The PL620-00 is an XO IC specifically designed to
work with high frequency fundamental and third
overtone crystals. Its design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. It
achieves very low current into the crystal resulting in
better overall stability. It is ideal for XO applications
requiring LVDS or PECL output levels at high
frequencies.
13
29
12
11
30
C502
31
1
2
3
4
5
6
7
8
10
9
GND
NC
Y
(0,0)
X
OUTPUT SELECTION AND ENABLE
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 m il
GND
80 m icron x 80 micron
10 m il
OUTSEL1
(Pad #18)
0
0
1
1
OE_SELECT
(Pad #9)
OUTSEL0
(Pad #25)
0
1
0
1
OE_CTRL
(Pad #30)
0
1 (Default)
0 (Default)
1
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
State
Tri-state
Output enabled
Output enabled
Tri-state
BLOCK DIAGRAM
SEL
OE
Vi
n
X+
X-
PLL by-pass
0
1 (Default)
Oscillator
Amplifier
PLL
(Phase
Locked
Loop)
Q
Q
Pad # 9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad # 30: Logical states defined by PECL levels if OE_SELECT (pad
# 9) is “1”
Logical states defined by CMOS levels if OE_SELECT is
“0”
PL620-00
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 5/10/07 Page 1
GNDBUF
GND
GND
GND
GND
GND
PL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
r d
O.T.)
FREQUENCY SELECTION TABLE
SEL3
(Pad #28)
1
1
1
SEL2
(Pad #29)
0
1
1
SEL1
(Pad #19)
1
1
1
SEL0
(Pad #20)
1
0
1
Selected Multiplier
Fin x 4
Fin x 2
No multiplication (no PLL)
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
C
C
C
C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested f or COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Interelectrode Capacitance
Recommended ESR
SYMBOL
F
XIN
C
L ( xtal)
C
0
R
E
CONDITIONS
Fundamental or 3
r d
overtone*
Die only
F
XIN
<160MHz and C0<3.0pF
F
XIN
<200MHz and C0<3.0pF
F
XIN
<200MHz and C0<2.5pF
MIN.
100
TYP.
MAX.
200
UNITS
MHz
pF
pF
3.0
3
30
25
30
* Note:
3
rd
overtone crystals require an external resistor between XIN and XOUT to prevent the fundamental from oscillating.
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
CONDITIONS
PECL/LVDS/CMOS
2.97
45
45
45
50
50
50
50
MIN.
TYP.
MAX.
100/80/40
3.63
55
55
55
UNITS
mA
V
%
mA
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 5/10/07 Page 2
PL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
r d
O.T.)
4. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-
peak
Random Jitter
Integrated jitter RMS at
155MHz
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-
peak
Random Jitter
Integrated jitter RMS at
622MHz
CONDITIONS
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5
18.5
2.5
24
2.5
0.3
11
45
11
24
3
1.6
MAX.
20
27
UNITS
ps
ps
ps
0.4
49
27
ps
ps
ps
ps
1.8
ps
Note: Higher Q factor of 3
r d
overtone crystals will result in even better jitter performance.
Measured on Wavecrest SIA 3000
5. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
155.52MHz
622.08MHz
@10Hz
-75
-75
@100Hz
-95
-95
@1kHz
-125
-110
@10kHz
-140
-125
@100kHz
-145
-120
UNITS
dBc/Hz
Note: Higher Q factor of 3
r d
overtone crystals will result in even better phase noise performance.
6. CMOS Electrical Specifications
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
I
OH
I
OL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
MIN.
30
30
10
10
TYP.
MAX.
UNITS
mA
mA
mA
mA
2.4
1.2
ns
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 5/10/07 Page 3
PL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
r d
O.T.)
7. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
V
OD
V
OH
V
OL
V
OS
V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
MAX.
454
50
1.6
1.375
25
10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
(see figure)
0.9
1.125
0
1.1
1.2
3
1
-5.7
V
out
= V
DD
or GND
V
DD
= 0V
8. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50
C
L
= 10pF
V
O D
V
O S
V
DIF F
R
L
= 100
50
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIF F
20%
0V
80%
20%
t
R
t
F
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 5/10/07 Page 4
PL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
r d
O.T.)
9. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
V
OH
V
OL
CONDITIONS
R
L
= 50
to
(V
DD
– 2V)
(see figure)
MIN.
V
DD
– 1.025
MAX.
V
DD
– 1.620
UNITS
V
V
10. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
t
r
t
f
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
TYP.
0.6
0.5
MAX.
1.5
1.5
UNITS
ns
ns
PECL Levels Test Circuit
OUT
VDD
OUT
PECL Output Skew
50
2.0V
50%
50
OUT
OUT
t
SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t
R
t
F
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 5/10/07 Page 5
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