256Mb, Twin-Quad I/O Serial Flash Memory
Features
Micron Serial NOR Flash Memory
3V, Twin-Quad I/O, 4KB, 32KB, 64KB, Sector Erase
MT25TL256
Features
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Stacked device (two 128Mb die)
SPI-compatible serial bus interface
Single and double transfer rate (STR/DTR)
Clock frequency
– 133 MHz (MAX) for all protocols in STR
– 90 MHz (MAX) for all protocols in DTR
Dual/quad I/O instruction provides increased
throughput up to 90 MB/s for each die correspond-
ing to 180 MB/s for the twin-quad device
Supported protocols: Extended, Dual and Quad I/O
both STR and DTR
Execute-in-place (XIP)
PROGRAM/ERASE SUSPEND operations
Volatile and nonvolatile configuration settings
Software reset
Additional reset pin for selected part numbers
Dedicated 64-byte OTP area outside main memory
– Readable and user-lockable
– Permanent lock with PROGRAM OTP command
Erase capability
– Die erase
– Sector erase 64KB uniform granularity
– Subsector erase 4KB, 32KB granularity
Erase performance: 400KB/sec (64KB sector)
Erase performance: 80KB/sec (4KB sub-sector)
Program performance: 2MB/sec
Security and write protection
– Volatile and nonvolatile locking and software
write protection for each 64KB sector
– Nonvolatile configuration locking
– Password protection
– Hardware write protection: nonvolatile bits
(BP[3:0] and TB) define protected area size
– Program/erase protection during power-up
– CRC detects accidental changes to raw data
Electronic signature
– JEDEC-standard 3-byte signature (BA18h)
– Extended device ID: two additional bytes identify
device factory options
JESD47H-compliant
– Minimum 100,000 ERASE cycles per sector
– Data retention: 20 years (TYP)
Options
• Voltage
– 2.7–3.6V
• Density
– 256Mb
• Device stacking
– B = 2 die and 1 S# pin
– H = 2 die and 2 S# pins
• Device generation
• Die revision
• Pin configuration
– RESET# and HOLD#
• Sector Size
– 64KB
• Packages – JEDEC-standard, RoHS-
compliant
– 16-pin SOP2, 300 mils body width
(SO16W)
– 24-ball T-PBGA, 05/6mm x 8mm
(TBGA24)
• Security Features
– Standard
• Special options
– Automotive
• Operating temperature range
– From –40°C to +105°C
Marking
L
256
B
H
B
A
8
E
SF
12
0
A
AT
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PDF: CCMTD-1725822587-3569
mt25t-qlhs-L256-xBA-xxT.pdf - Rev. H 07/18 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
256Mb, Twin-Quad I/O Serial Flash Memory
Features
Part Number Ordering
Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers
by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Number Ordering Information
MT 25T
Micron Technology
Part Family
25T = Twin Quad Serial NOR Flash
Voltage
L = 2.7–3.6V
L
xxx
B
BA
1
E
SF - 0
A
AT ES
Production Status
Blank = Production
ES = Engineering samples
QS = Qualification samples
Operating Temperature
AT = –40°C to +105°C
Density
256 = 256Mb (32MB)
512 = 512Mb (64MB)
01G = 1Gb (128GB)
Stack
B = 2 die/1 S#
H = 2 die/2 S#
Device Generation
A = 1st generation
B = 2nd generation
Die Revision
A = Rev. A
B = Rev. B
Special Options
A = Automotive grade AEC-Q100
Security Features
0 = Standard default security
Package Codes
12 = 24-ball T-PBGA, 05/6 x 8mm (5 x 5 array)
SF = 16-pin SOP2, 300 mil
Sector size
E = 64KB sectors, 4KB and 32KB sub-sectors
Pin Configuration Option
1 = HOLD# pin
3 = RESET# pin
8 = RESET# and HOLD# pins
PDF: CCMTD-1725822587-3569
mt25t-qlhs-L256-xBA-xxT.pdf - Rev. H 07/18 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
256Mb, Twin-Quad I/O Serial Flash Memory
Features
Contents
Important Notes and Warnings ......................................................................................................................... 8
Device Description ........................................................................................................................................... 9
Block Diagram ............................................................................................................................................ 10
Advanced Security Protection ..................................................................................................................... 11
Device Logic Diagram ................................................................................................................................. 12
Signal Assignments ......................................................................................................................................... 13
Signal Descriptions ......................................................................................................................................... 16
Package Dimensions – Package Code: SF ......................................................................................................... 17
Package Dimensions – Package Code: 12 ......................................................................................................... 18
Memory Map – 128Mb Density ....................................................................................................................... 19
Status Register ................................................................................................................................................ 20
Block Protection Settings ............................................................................................................................ 21
Flag Status Register ......................................................................................................................................... 22
Internal Configuration Register ....................................................................................................................... 23
Nonvolatile Configuration Register .................................................................................................................. 24
Volatile Configuration Register ........................................................................................................................ 25
Supported Clock Frequencies ..................................................................................................................... 26
Enhanced Volatile Configuration Register ........................................................................................................ 28
Security Registers ........................................................................................................................................... 29
Sector Protection Security Register .................................................................................................................. 30
Nonvolatile and Volatile Sector Lock Bits Security ............................................................................................ 31
Volatile Lock Bit Security Register .................................................................................................................... 31
Device ID Data ............................................................................................................................................... 32
Serial Flash Discovery Parameter Data ............................................................................................................. 33
Command Definitions .................................................................................................................................... 34
Software RESET Operations ............................................................................................................................ 38
RESET ENABLE and RESET MEMORY Commands ....................................................................................... 38
READ ID Operations ....................................................................................................................................... 40
READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 40
READ SERIAL FLASH DISCOVERY PARAMETER Operation .............................................................................. 41
READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 41
READ MEMORY Operations ............................................................................................................................ 42
READ MEMORY Operations Timings ............................................................................................................... 43
WRITE ENABLE/DISABLE Operations ............................................................................................................. 49
READ REGISTER Operations ........................................................................................................................... 50
WRITE REGISTER Operations ......................................................................................................................... 52
CLEAR FLAG STATUS REGISTER Operation ..................................................................................................... 54
PROGRAM Operations .................................................................................................................................... 55
PROGRAM Operations Timings ....................................................................................................................... 56
ERASE Operations .......................................................................................................................................... 59
SUSPEND/RESUME Operations ..................................................................................................................... 61
PROGRAM/ERASE SUSPEND Operations .................................................................................................... 61
PROGRAM/ERASE RESUME Operations ...................................................................................................... 61
ONE-TIME PROGRAMMABLE Operations ....................................................................................................... 63
READ OTP ARRAY Command ...................................................................................................................... 63
PROGRAM OTP ARRAY Command .............................................................................................................. 63
DEEP POWER-DOWN Operations ................................................................................................................... 64
ENTER DEEP POWER-DOWN Command .................................................................................................... 64
RELEASE FROM DEEP POWER-DOWN Command ....................................................................................... 65
DEEP POWER-DOWN Timings .................................................................................................................... 66
PDF: CCMTD-1725822587-3569
mt25t-qlhs-L256-xBA-xxT.pdf - Rev. H 07/18 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
256Mb, Twin-Quad I/O Serial Flash Memory
Features
QUAD PROTOCOL Operations ........................................................................................................................
ENTER or RESET QUAD INPUT/OUTPUT MODE Command .......................................................................
CYCLIC REDUNDANCY CHECK Operations ....................................................................................................
State Table .....................................................................................................................................................
XIP Mode .......................................................................................................................................................
Activate or Terminate XIP Using Volatile Configuration Register ...................................................................
Activate or Terminate XIP Using Nonvolatile Configuration Register .............................................................
Confirmation Bit Settings Required to Activate or Terminate XIP ..................................................................
Terminating XIP After a Controller and Memory Reset .................................................................................
Power-Up and Power-Down ............................................................................................................................
Power-Up and Power-Down Requirements ..................................................................................................
Active, Standby, and Deep Power-Down Modes ................................................................................................
Power Loss and Interface Rescue .....................................................................................................................
Recovery ....................................................................................................................................................
Power Loss Recovery ...................................................................................................................................
Interface Rescue .........................................................................................................................................
Absolute Ratings and Operating Conditions .....................................................................................................
DC Characteristics and Operating Conditions ..................................................................................................
AC Characteristics and Operating Conditions ..................................................................................................
AC Reset Specifications ...................................................................................................................................
Program/Erase Specifications .........................................................................................................................
Revision History .............................................................................................................................................
Rev. H – 07/18 .............................................................................................................................................
Rev. G – 06/18 .............................................................................................................................................
Rev. F – 06/16 .............................................................................................................................................
Rev. E – 06/16 .............................................................................................................................................
Rev. D – 03/16 .............................................................................................................................................
Rev. C – 12/15 .............................................................................................................................................
Rev. B – 01/15 .............................................................................................................................................
Rev. A – 11/14 .............................................................................................................................................
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PDF: CCMTD-1725822587-3569
mt25t-qlhs-L256-xBA-xxT.pdf - Rev. H 07/18 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
256Mb, Twin-Quad I/O Serial Flash Memory
Features
List of Figures
Figure 1: Part Number Ordering Information .................................................................................................... 2
Figure 2: Block Diagram – Flash Die 1 ............................................................................................................. 10
Figure 3: Block Diagram – Flash Die 2 ............................................................................................................. 11
Figure 4: Logic Diagram – Separate Chip-Select and Clock Signals ................................................................... 12
Figure 5: Logic Diagram – Shared Chip-Select and Clock Signals ..................................................................... 12
Figure 6: 16-Pin, Plastic Small Outline – SO16 (Top View) (Single Chip-Select and Clock) ................................. 13
Figure 7: 16-Pin, Plastic Small Outline – SO16 (Top View) (Dual Chip-Select and Clock) ................................... 13
Figure 8: 24-Ball TBGA – 5 x 5 (Balls Down) (Single Chip-Select and Clock) ...................................................... 14
Figure 9: 24-Ball TBGA – 5 x 5 (Balls Down) (Double Chip-Select and Clock) .................................................... 15
Figure 10: 16-Pin SOP2 – 300 Mils Body Width ................................................................................................ 17
Figure 11: 24-Ball T-PBGA (5 x 5 ball grid array) – 6mm x 8mm ........................................................................ 18
Figure 12: Internal Configuration Register ...................................................................................................... 23
Figure 13: Sector and Password Protection ..................................................................................................... 29
Figure 14: RESET ENABLE and RESET MEMORY Command ........................................................................... 39
Figure 15: READ ID and MULTIPLE I/O READ ID Commands ......................................................................... 40
Figure 16: READ SERIAL FLASH DISCOVERY PARAMETER Command – 5Ah ................................................... 41
Figure 17: READ – 03h ................................................................................................................................... 43
Figure 18: FAST READ – 0Bh .......................................................................................................................... 43
Figure 19: DUAL OUTPUT FAST READ – 3Bh .................................................................................................. 44
Figure 20: DUAL INPUT/OUTPUT FAST READ – BBh ..................................................................................... 44
Figure 21: QUAD OUTPUT FAST READ – 6Bh ................................................................................................. 45
Figure 22: QUAD INPUT/OUTPUT FAST READ – EBh ..................................................................................... 45
Figure 23: QUAD INPUT/OUTPUT WORD READ – E7h ................................................................................... 46
Figure 24: DTR FAST READ – 0Dh .................................................................................................................. 46
Figure 25: DTR DUAL OUTPUT FAST READ – 3Dh .......................................................................................... 47
Figure 26: DTR DUAL INPUT/OUTPUT FAST READ – BDh ............................................................................. 47
Figure 27: DTR QUAD OUTPUT FAST READ – 6Dh ......................................................................................... 48
Figure 28: DTR QUAD INPUT/OUTPUT FAST READ – EDh ............................................................................. 48
Figure 29: WRITE ENABLE and WRITE DISABLE Timing ................................................................................. 49
Figure 30: READ REGISTER Timing ................................................................................................................ 50
Figure 31: WRITE REGISTER Timing .............................................................................................................. 53
Figure 32: CLEAR FLAG STATUS REGISTER Timing ........................................................................................ 54
Figure 33: PAGE PROGRAM Command .......................................................................................................... 56
Figure 34: DUAL INPUT FAST PROGRAM Command ...................................................................................... 56
Figure 35: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 57
Figure 36: QUAD INPUT FAST PROGRAM Command ..................................................................................... 57
Figure 37: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 58
Figure 38: SUBSECTOR and SECTOR ERASE Timing ....................................................................................... 60
Figure 39: BULK ERASE Timing ...................................................................................................................... 60
Figure 40: PROGRAM/ERASE SUSPEND or RESUME Timing .......................................................................... 62
Figure 41: READ OTP Command .................................................................................................................... 63
Figure 42: PROGRAM OTP Command ............................................................................................................ 64
Figure 43: ENTER DEEP POWER-DOWN Timing ............................................................................................. 66
Figure 44: RELEASE FROM DEEP POWER-DOWN Timing ............................................................................... 67
Figure 45: XIP Mode Directly After Power-On .................................................................................................. 72
Figure 46: Power-Up Timing .......................................................................................................................... 75
Figure 47: AC Timing Input/Output Reference Levels ...................................................................................... 79
Figure 48: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 85
Figure 49: Reset Enable and Reset Memory Timing ......................................................................................... 85
Figure 50: Serial Input Timing STR ................................................................................................................. 85
PDF: CCMTD-1725822587-3569
mt25t-qlhs-L256-xBA-xxT.pdf - Rev. H 07/18 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
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