74AVC16373
Rev. 3 — 20 February 2018
16-bit D-type transparent latch; 3.6 V tolerant; 3-state
Product data sheet
1
General description
The 74AVC16373 is a 16-bit D-type transparent latch featuring separate D-type inputs
for each latch and 3-state outputs for bus oriented applications. One latch enable (LE)
input and one output enable (OE) input are provided per 8-bit section. The 74AVC16373
consist of two sections of eight D-type transparent latches with 3-state true outputs.
The 74AVC16373 is designed to have an extremely fast propagation delay and a
minimum amount of power consumption.
To ensure the high-impedance output state during power-up or power-down, pin nOE
should be tied to V
CC
through a pull-up resistor (Live Insertion).
A dynamic controlled output (DCO) circuitry is implemented to support termination line
drive during transient (see
Figure 5).
2
Features and benefits
•
Wide supply voltage range from 1.2 V to 3.6 V
•
Complies with JEDEC standards:
–
JESD8-7 (1.2 V to 1.95 V)
–
JESD8-5 (1.8 V to 2.7 V)
–
JESD8-1A (2.7 V to 3.6 V)
•
CMOS low power consumption
•
Input/output tolerant up to 3.6 V
•
Dynamic Controlled Output (DCO) circuit dynamically changes output impedance,
resulting in noise reduction without speed degradation
•
Low inductance multiple V
CC
and GND pins to minimize noise and ground bounce
•
Supports Live Insertion
3
Ordering information
Package
Temperature range Name
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT362-1
−40 °C to +85 °C
TSSOP48
Table 1. Ordering information
Type number
74AVC16373DGG
Nexperia
16-bit D-type transparent latch; 3.6 V tolerant; 3-state
74AVC16373
4
Functional diagram
1OE
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
mgu770
1EN
C3
2EN
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1
1OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1LE
48
24
2OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2LE
25
001aam007
1LE
2OE
2LE
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
Figure 1. Logic symbol
1D0
D
Q
1Q0
Figure 2. IEC logic symbol
2D0
D
Q
2Q0
LATCH
1
LE
LE
LATCH
9
LE
LE
1LE
1OE
to 7 other channels
2LE
2OE
to 7 other channels
mgu769
Figure 3. Logic diagram
74AVC16373
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 20 February 2018
2 / 15
Nexperia
16-bit D-type transparent latch; 3.6 V tolerant; 3-state
74AVC16373
5
Pinning information
5.1 Pinning
74AVC16373
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48 1LE
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 V
CC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 V
CC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2LE
aaa-028180
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
V
CC
18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
Figure 4. Pin configuration SOT362-1 (TSSOP48)
5.2 Pin description
Table 2. Pin description
Symbol
1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7
2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7
1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7
2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7
1OE, 2OE
1LE, 2LE
GND
V
CC
Pin
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
1, 24
48, 25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
Description
data inputs
data inputs
data outputs
data outputs
output enable inputs (active LOW)
latch enable inputs (active HIGH)
ground (0 V)
supply voltage
74AVC16373
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 20 February 2018
3 / 15
Nexperia
16-bit D-type transparent latch; 3.6 V tolerant; 3-state
74AVC16373
6
Functional description
[1]
Table 3. Function table
Operating mode
Inputs
nOE
nLE
H
H
↓
↓
L
L
H
nDn
L
H
l
h
X
X
nDn
L
L
L
L
L
H
H
Internal
latches
L
H
L
H
NC
NC
nDn
Outputs
nQn
L
H
L
H
NC
Z
Z
enable and read register (transparent mode)
latch and read register
Hold
Latch register and disable outputs
[1] H = HIGH voltage level;
L = LOW voltage level;
↓ = HIGH-to-LOW LE transition;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
NC = No change;
Z = high-impedance OFF-state.
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
= −40 °C to +85 °C
[2]
Conditions
V
I
< 0 V
data and control inputs
V
O
< 0 V
output HIGH or LOW
output 3-state
V
O
= 0 V to V
CC
[1]
[1]
[1]
Min
-0.5
-
-0.5
-
-0.5
-0.5
-
-
-100
-65
-
Max
+4.6
-50
+4.6
-50
+4.6
+50
100
-
+150
500
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
CC
+ 0.5 V
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
74AVC16373
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 20 February 2018
4 / 15
Nexperia
16-bit D-type transparent latch; 3.6 V tolerant; 3-state
74AVC16373
8
Recommended operating conditions
Conditions
for low-voltage applications
according to JEDEC Low Voltage
Standards
Min
1.2
1.4
1.65
2.3
3.0
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
3.6
1.6
1.95
2.7
3.6
3.6
V
CC
3.6
+85
40
30
20
10
Unit
V
V
V
V
V
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
Table 5. Recommended operating conditions
Symbol Parameter
V
CC
supply voltage
V
I
V
O
T
amb
Δt/ΔV
input voltage
output voltage
ambient temperature
input transition rise and fall rate
output HIGH or LOW
output 3-state
in free air
V
CC
= 1.4 V to 1.6 V
V
CC
= 1.65 V to 2.3 V
V
CC
= 2.3 V to 3.0 V
V
CC
= 3.0 V to 3.6 V
0
0
0
−40
0
0
0
0
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions; T
amb
= −40 °C to +85 °C; Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input
voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.4 V to 1.6 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input
voltage
V
CC
= 1.2 V
V
CC
= 1.4 V to 1.6 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
; see
Figure 5
I
O
= -100 μA; V
CC
= 1.65 V to 3.6 V
I
O
= -3 mA; V
CC
= 1.4 V
I
O
= -4 mA; V
CC
= 1.65 V
I
O
= -8 mA; V
CC
= 2.3 V
I
O
= -12 mA; V
CC
= 3.0 V
V
CC
- 0.20
V
CC
- 0.35
V
CC
- 0.45
V
CC
- 0.55
V
CC
- 0.70
V
CC
V
CC
- 0.23
V
CC
- 0.25
V
CC
- 0.38
V
CC
- 0.48
-
-
-
-
-
V
V
V
V
V
Min
V
CC
0.65 × V
CC
0.65 × V
CC
1.7
2.0
-
-
-
-
-
Typ
-
0.9
0.9
1.2
1.5
-
0.9
0.9
1.2
1.5
[1]
Max
-
-
-
-
-
GND
0.35 × V
CC
0.35 × V
CC
0.7
0.8
Unit
V
V
V
V
V
V
V
V
V
V
74AVC16373
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 20 February 2018
5 / 15
NXP MCU
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