MC74HCT132A
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
with LSTTL Compatible
Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
The MC74HCT132A can be used to enhance noise immunity or to
square up slowly changing waveforms.
Features
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
HCT132AG
AWLYWW
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements as Defined by JEDEC
Standard No. 7A
•
Chip Complexity: 72 FETs or 18 Equivalent Gates
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
A1
B1
Y1
A2
B2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
B4
A4
Y4
B3
A3
Y3
14
TSSOP−14
DT SUFFIX
CASE 948G
1
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
HCT
132A
ALYWG
G
FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Figure 1. Pin Assignment
©
Semiconductor Components Industries, LLC, 2009
1
September, 2016 − Rev. 2
Publication Order Number:
MC74HCT132A/D
MC74HCT132A
A1
1
3
B1
A2
2
4
6
B2
A3
5
Y = AB
9
8
B3
10
Y3
Y2
Y1
A4 12
11
B4
13
PIN 14 = V
CC
PIN 7 = GND
Y4
Figure 2. Logic Diagram
ORDERING INFORMATION
Device
MC74HCT132ADG
MC74HCT132ADR2G
NLV74HCT132ADR2G*
MC74HCT132ADTR2G
NLVHCT132ADTR2G*
TSSOP−14
(Pb−Free)
SOIC−14
(Pb−Free)
Package
Shipping
†
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC74HCT132A
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
Positive DC Supply Voltage
Digital Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Above V
CC
and Below GND at 85_C (Note 4)
14−SOIC
14−TSSOP
SOIC
TSSOP
Output in 3−State
High or Low State
Parameter
Value
*0.5
to
)7.0
*0.5
to
)7.0
*0.5
to
)7.0
*0.5
to V
CC
)0.5
*20
$20
$25
$75
$75
*65
to
)150
260
)150
125
170
500
450
Level 1
UL 94 V0 @ 0.125 in
u2000
u100
u500
$300
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
I
Latch−Up
Latch−Up Performance
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 3)
Min
2.0
0
*55
−
Max
6.0
V
CC
)125
No Limit
(Note 5)
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. When V
IN
X
0.5 V
CC
, I
CC
>> quiescent current.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
MC74HCT132A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
T+
max
V
T+
min
V
T–
max
V
T–
min
V
H
min
(Note 7)
V
OH
Parameter
Maximum Positive−Going
Input Threshold Voltage
Minimum Positive−Going
Input Threshold Voltage
Maximum Negative−Going
Input Threshold Voltage
Minimum Negative−Going
Input Threshold Voltage
Minimum Hysteresis
Voltage
Minimum High−Level
Output Voltage
Test Conditions
V
OUT
= 0.1 V
|I
OUT
|
v
20
mA
V
OUT
= 0.1 V
|I
OUT
|
v
20
mA
V
OUT
= V
CC
– 0.1 V
|I
OUT
|
v
20
mA
V
OUT
= V
CC
– 0.1 V
|I
OUT
|
v
20
mA
V
OUT
= 0.1 V or V
CC
– 0.1 V
|I
OUT
|
v
20
mA
V
IN
v
V
T−
min or V
T+
max
|I
OUT
|
v
20
mA
V
IN
v
−V
T−
min or V
T+
max
|I
OUT
|
v
4.0 mA
V
OL
Maximum Low−Level
Output Voltage
V
IN
≥
V
T+
max
|I
OUT
|
v
20
mA
V
IN
≥
V
T+
max
I
IN
I
CC
Maximum Input Leakage
Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
= V
CC
or GND
V
IN
= V
CC
or GND
I
OUT
= 0
mA
|I
OUT
|
v
4.0 mA
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
Guaranteed Limit
*55_C
to 25_C
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
0.4
0.4
4.4
5.4
3.98
0.1
0.1
0.26
$0.1
1.0
v85_C
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
0.4
0.4
4.4
5.4
3.84
0.1
0.1
0.33
$1.0
10
v125_C
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
0.4
0.4
4.4
5.4
3.7
0.1
0.1
0.4
$1.0
40
mA
mA
V
Unit
V
V
V
V
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. V
H
min
u
(V
T+
min)
*
(V
T−
max); V
H
max = (V
T+
max)
)
(V
T−
min).
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns, V
CC
= 5.0 V
±
10%)
V
CC
Symbol
t
PLH
,
t
PHL
t
TLH
,
t
THL
C
in
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
Maximum Input Capacitance
V
5.0
5.0
—
Guaranteed Limit
*55_C
to 25_C
25
15
10
v85_C
31
19
10
v125_C
38
22
10
Unit
ns
ns
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (per Gate) (Note 8)
24
pF
8. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
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4
MC74HCT132A
TEST POINT
t
r
INPUT
A OR B
(V
I
)
90%
V
M
10%
t
PHL
90%
V
M
10%
t
THL
V
I
= GND to 3.0 V
V
M
= 1.3 V
t
TLH
*Includes all probe and jig capacitance
t
PLH
t
f
V
CC
GND
DEVICE
UNDER
TEST
OUTPUT
C
L
*
Y
Figure 3. Switching Waveforms
Figure 4. Test Circuit
V
CC
V
H
V
IN
V
T +
V
T -
GND
V
OH
V
IN
V
H
V
CC
V
T +
V
T -
GND
V
OH
V
OUT
V
OL
V
CC
V
OUT
V
OL
V
IN
(a) A SCHMITT TRIGGER SQUARES UP INPUTS
(a)
WITH SLOW RISE AND FALL TIMES
V
OUT
(b) A SCHMITT TRIGGER OFFERS MAXIMUM
NOISE IMMUNITY
Figure 5. Typical Schmitt−Trigger Applications
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