CTM8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
FEATURES
• Total of 33 single word instructions .
• The fast execution time may be 200ns for all single
cycle instructions under 20MHz operating.
• Operating voltage range: 2.3V ~ 6.5V
• 8-bit data bus.
• 14-bit instruction word.
• Four-level stacks.
• On chip EPROM size : 512x14 bits for CTM8B54E/55E,
1Kx14 bits for CTM8B56E,
2Kx14 bits for CTM8B57E.
• Internal RAM size : 25 bytes for CTM8B54E/56E,
24 bytes for CTM8B55E,
•
72 bytes for CTM8B57E.
• Direct and indirect addressing modes for data accessing
• 8-bit real time clock/counter with 8-bit programmable
prescaler.
• Internal power-on Reset.
• Device Reset Timer.
• Code protection.
• Sleep mode for power saving.
• On chip Watchdog Timer(WDT) based on internal RC
oscillator.
• Three I/O ports PA, PB nad PC with independent direc-
tion control.
• 4 types of oscillator can be selected by code options:
- RC : Low-cost RC oscillator
- XTAL : Standard crystal oscillator
- HFXTAL : High frequency crystal oscillator
- LFXTAL : Low frequency crystal oscillator
GENERAL DESCRIPTION
CTM8B5X series is an EPROM based 8-bit micro-
controller which employs a full CMOS technology
enhanced with low-cost, high speed and high noise
immunity. Watchdog Timer, RAM, EPROM, tri-state
I/O port, power down mode, and real time program-
mable clock/counter are integrated into this chip.
CTM8B5X contains 33 instructions, all are single
cycle except for program branches which take two
cycles.
On chip memory is available with 512x14 bits of
EPROM for CTM8B54E/55E, 1Kx14 bits of EPROM
for CTM8B56E, 2Kx14 bits of EPROM for
CTM8B57E and 24 to 72 bytes of static RAM.
BLOCK DIAGRAM
V
dd
V
ss
Configuration
Word
Osc Mode
2 Select
Four-level
Stack
11
Program
Counter
11
Enable
/Disable
OSCI
OSCO
MCLR
Sleep
WatchDog
Timer
Oscillator
Circuit
EPROM
512 X 14 TO
2048 X 14
14
Instruction
Register
T0CKI
WDT/Timer0
Prescaler
6
WDT
Time Out
14
Timer0
Data
Instruction
Decoder
4
T0MODE
Register
6
8
RAM
24, 25 or 27 Bytes
PortA
PA3:PA0
Accumulator
FSR
PortB
8
PB7:PB0
PortC
Status
ALU
8
Only in CTM8B55E/57E
8
PC7:PC0
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
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Tel:886-3-3529445
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CTM8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
1.0 PIN CONNECTION
T0CKI
Vdd
PA2
PA3
T0CKI
MCLR/Vpp
Vss
PB0
PB1
PB2
PB3
1
2
3
4
5
CTM8B54E
6
CTM8B56E
7
8
9
18
17
16
15
14
13
12
11
10
PA1
PA0
OSCI
OSCO
Vdd
PB7
PB6
PB5
PB4
N/C
Vss
N/C
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PB4
1
2
3
4
5
6
7
CTM8B55E
8
CTM8B57E
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/Vpp
OSCI
OSCO
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
2.0 PIN DESCRIPTIONS
Name
OSCI
I/O
I
Descriptions
RC type: Input pin of RC oscillator
XTAL type: Input terminal of crystal oscillator
RC type: OSCO outputs with 1/4 frequency of OSCI to denotes the cycle
rate for instruction.
XTAL type: Output terminal of crystal oscillator
OSCO
T0CKI/SCL
O
I
Input pin of real time counter/clock. Must be tied to Vss or Vdd if not in use.
Input pin for device reset or high voltage programming input for EPROM. If
this pin is low, the device is reset.
MCLR/Vpp
I
In programmimg mode, this pin is connected to 12V. In normal operating
mode, this pin must not exceed Vdd to avoid entering unintended program-
ming mode.
PA0~PA3 as bi-directional I/O port
PB0~PB7 as bi-directional I/O port
PC0~PC7 as bi-directional I/O port
Power supply
Ground
PA0~PA3
PB0~PB7
PC0~PC7
Vdd
Vss
I/O
I/O
I/O
-
-
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
Http: www.ceramate.com.tw
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Rev 1.1 Dec 26,2001
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CTM8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
3.0 FUNCTIONAL DESCRIPTIONS
3.1 REGISTER MAP
The register map of CTM8B5X is depicted as below:.
The Register Map of CTM8B54E/56E
Address
00h
01h
02h
03h
04h
05h
06h
07h-1Fh
Description
Indirect Addressing Register
Timer0
PC
STATUS
FSR
PORTA
PORTB
General Purpose Register
The Register Map of CTM8B55E
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h-1Fh
The Register Map of CTM8B57E
Address
FSR<6:5>
00h
01h
02h
03h
04h
05h
06h
07h
08h~0Fh
Bank 0
00
Indirect Address-
ing Register
Timer0
PC
STATUS
FSR
PORTA
PORTB
PORTC
General Purpose
Register
10h~1Fh
General Purpose
Register
30h~3Fh
General Purpose
Register
50h~5Fh
General Purpose
Register
70h~7Fh
General Purpose
Register
Map back to address in Bank 0
Bank 1
01
Description
Bank 2
10
Bank 3
11
Description
Indirect Addressing Register
Timer0
PC
STATUS
FSR
PORTA
PORTB
PORTC
General Purpose Register
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
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Tel:886-3-3529445
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CTM8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
3.1.1 INAR(Indirect Address Register) : R0
R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction
accessing this register can access data pointed by FSR(R4).
3.1.2 Timer0(8-bit real-time clock/timer) : R1
This register increases by an external signal edge applied to T0CKI pin, or by internal instruction cycle. It can
be read or written as any other register.
3.1.3 PC(Program Counter) : R2
This register increases itself every instruction cycle, except the following condition shown in Figure 1:
LCALL, LGOTO : from instruction word
RETIA : from STACK
LCALL
A10~A0
RETIA
FIGURE 1. Program Counter
3.1.4 STATUS(Status Register):
The content of R3 is listed in Table 1.
TABLE 1. STATUS Register
Bit
Symbol
Carry/borrow bit
ADDWF
0
C
= 1, a carry occurred
= 0, a carry did not occur
Half carry/half borrow bit
ADDWF
= 1, a carry from the 4th low order bit of the result occurred
1
DC
= 0, a carry from the 4th low order bit of the result did not occur
SUBWF
= 1, a borrow from the 4th low order bit of the result did not occur
= 0, a borrow from the 4th low order bit of the result occurred
Zero bit:
2
Z
= 1, the result of a logic operation is zero
= 0, the result of a logic operation is not zero
Power down flag bit:
3
PD
= 1, after power-up or by the CLRWDT instruction
= 0, by the SLEEP instruction
Time overflow flag bit:
4
5, 6, 7
TO
-
= 1, after power-up or by the CLRWDT or SLEEP instruction
= 0, a WDT time-overflow occurred
Unused
Description
SUBWF
= 1, a borrow did not occur
= 0, a borrow occurred
Stack1
Stack2
Stack3
Stack4
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
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CTM8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
3.1.5 FSR(File select register pointer): R4
Bit 0~4 are used to select up to 32 registers (address: 00h~1Fh) and Bit 5~6 are Bank Select (Bank0~3) in the
indirect addressing mode shown in Figure 2.
3.1.6 PORT A: R5
PA3:PA0, bi-directional I/O Register
3.1.7 PORT B: R6
PB7:PB0, bi-directional I/O Register
3.1.8 PORT C: R7
PB7:PB0, bi-directional I/O Register, and for MTU8B55E/57E only
3.1.9 T0MODE REGISTER:
T0MODE is a write-only register and the content is listed in Table 2.
3.1.10 IOST (Control Port I/O Mode Register)
The IOST register is “write-only”
= 0, I/O pin in output mode;
= 1, I/O pin in input mode.
Bank Select
Indirect Addressing Mode
Location Select
B7
B6
B5
B4
B3
B2
B1
B0
Read 1
70h
Bank 3
50h
Bank 2
30h
Bank 1
Bank 0
10h
16 Bytes
SRAM
7Fh
5Fh
3Fh
1Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
0Fh
INAR
Timer0
PC
STATUS
FSR
PORT A
PORT B
PORT C
8 Bytes
SRAM
Bank 0
FIGURE 2. Data Memory Configuraion
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
Http: www.ceramate.com.tw
Page 5 of
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Rev 1.1 Dec 26,2001
Fax:886-3-3521052