UATM30M2C Datasheet
CENTELLAX
0.04 - 30GHz Broadband MMIC
Low-Noise Amplifier
Application
The UATM30M2C Broadband MMIC Low-Noise
Amplifier is designed for low-noise and broadband
flat-gain applications in RF and microwave commu-
nications, test equipment and military systems. By
using specific external components, the bandwidth
of operation can be extended below 40MHz.
Device Highlights
•
Low noise, ultra-flat gain 6-20GHz:
•
2.5dB NF, 18 ± 0.3dB gain
•
Excellent 1.5-20GHz performance:
•
Very flat gain (18 ± 0.6dB)
•
High P
sat
at 20GHz (20dBm)
•
High P
-1dB
at 20GHz (17dBm)
•
Wideband operation: 0.04-30GHz
•
Good input / output return loss
•
High isolation
•
>30dB dynamic gain control
•
Integrated power detector
•
100% DC, RF, and visually tested
•
Size: 2390x920um (94.1x36.2mil)
Description
The UATM30M2C is an eight stage traveling wave
amplifier. The amplifier has been designed for low
noise, flat gain, and good return loss to 30GHz. The
amplifier typically has 2.5dB NF and 18dB gain from
6-20GHz, and 16dB gain from 0.04-30GHz.
Features
The UATM30M2C has >30dB dynamic gain control,
and includes a temperature-referenced power detec-
tor output.
Key Specifications
Vdd=5.0V, Idd=150mA, Zo=50Ω
Specifications pertain to wafer measurements with RF probes and DC bias cards @ 25°C
6 - 20GHz
Parameter
S21 (dB)
Flatness (±dB)
S11 (dB)
S22 (dB)
S12 (dB)
1.5 - 20GHz
Max
Min
16.5
0.6
-13
-15
-30
16
19
17
0.04 - 30GHz
Min
14.5
1.0
-13
-15
-30
12
14
Description
Small Signal Gain
Gain Flatness
Input Match
Output Match
Reverse Isolation
Min
16.5
Typ
18
0.3
-16
-18
-35
17
20
18.5
2.5
0.5
Typ
18
0.6
-16
-18
-35
17
20
18.5
5
0.5
Max
Typ
16
1.5
-10
-18
-30
13.5
16.5
Max
2.0
-8
-15
-25
P
-1dB
(dBm)
1dB Compressed Output Power
P
sat
(dBm)
Saturated Output Power
P
out
@16dB (dBm) Output Power at 16dB Gain
NF (dB)
RF
det
(mV/mW)
Noise Figure
RF Detector Sensitivity
16
19
17
5.5
0.5
CENTELLAX
• Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. Copyright © 2001-2006 Centellax, Inc. Printed in USA. 19 Apr 2006.
UATM30M2C S21
20
6
UATM30M2C Noise Figure
5
15
4
S21 (dB)
NF (dB)
5V, 150mA
7V, 190mA
10
3
2
5
1
5V, 150mA
7V, 190mA
4.3V, 90mA
0
0
5
10
15
Frequency (GHz)
20
25
30
0
0
5
10
15
Frequency (GHz)
20
25
30
Typical IC performance measured on-wafer
UATM30M2C S11, S22
0
5V, 150mA S11
7V, 190mA S11
5V, 150mA S22
7V, 190mA S22
Typical IC performance with package de-embedded
UATM30M2C S12
0
5V, 150mA
7V, 190mA
-5
-10
S11, S22 (dB)
-10
S12 (dB)
0
5
10
15
Frequency (GHz)
20
25
30
-20
-15
-30
-20
-40
-25
-30
-50
0
5
10
15
Frequency (GHz)
20
25
30
Typical IC performance measured on-wafer
UATM30M2C Output Power
26
24
Output Power (dBm)
22
20
18
16
14
12
0
5
10
15
Frequency (GHz)
20
25
30
80
70
60
Group Delay (ps)
50
40
30
20
10
0
Typical IC performance measured on-wafer
UATM30M2C Group Delay
8V,
7V,
6V,
5V,
200mA Psat
190mA Psat
170mA Psat
150mA Psat
8V,
7V,
6V,
5V,
200mA P-1
190mA P-1
170mA P-1
150mA P-1
5V, 150mA
7V, 190mA
0
5
10
15
Frequency (GHz)
20
25
30
Typical IC performance measured on-wafer
Typical IC performance measured on-wafer
Typical measurement data is available upon request. Email support@centellax.com for more information.
CENTELLAX
• Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Supplemental Specifications
Parameter
Vdd
Idd
Vg1
Vg2
P
in
P
dc
T
ch
Θ
ch
Description
Drain Bias Voltage
Drain Bias Current
1st Gate Bias Voltage
2nd Gate Bias Voltage
Input Power (CW)
Power Dissipation
Channel Temperature
Thermal Resistance (T
case
=85°C)
Min
3V
—
-4V
Vdd-Vg2<7V
Typ
5V
150mA
—
N/C
Max
8V
250mA
0V
+4V
20dBm
0.75W
150°C
18°C/W
Low-Frequency Use
The UATM30M2C has been
designed so that the bandwidth
can be extended to low frequen-
cies. The low end corner fre-
quency of the device is primarily
determined by the external bias-
ing and AC coupling circuitry.
Matching
The amplifier incorporates on-
chip termination resistors on the
RF input and output. These resis-
tors are RF grounded through on-
chip capacitors, which are small
and become open circuits at fre-
quencies below 1GHz.
A pair of gate and drain termina-
tion bypass pads are provided for
connecting external capacitors
required for the low frequency
extension network. These capac-
itors should be 10x the value of
the DC blocking capacitors.
DC Bias
The UATM30M2C is biased by apply-
ing a positive voltage to the drain
(Vdd), then setting the drain current
(Idd) using a negative voltage on the
gate (Vg1).
When zero volts is applied to the gate,
the drain to source channel is open;
this results in high Idd. When Vg1 is
biased negatively, the channel is
pinched off and Idd decreases.
The nominal bias is Vdd=5.0V,
Idd=150mA. Improved noise or power
performance can be achieved with
application-specific biasing.
Gain Control
Dynamic gain control is available
when operating the amplifier in
the linear gain region. Negative
voltage applied to the second
gate (Vg2) reduces amplifier gain.
RF Power Detection
RF output power can be calcu-
lated from the difference between
the RF detector voltage and the
DC detector voltage, minus a DC
offset. Please consult the power
detector application note avail-
able from the Centellax webpage.
DC Blocks
The amplifier is DC coupled to the
RF input and output pads; DC
voltage on these pads must be
isolated from external circuitry.
For operation above 2GHz, a
series DC-blocking capacitor with
minimum value of 20pF is recom-
mended; operation above 40MHz
requires a minimum of 120pF.
Inductor Bias
DC bias applied to the drain (Vdd)
must be decoupled with an off-
chip RF choke inductor. The
amount of bias inductance will
determine the low frequency
operating point. Inductive biasing
can also be applied to the chip
through the RF output.
For many applications above
2GHz, a bondwire from the Vdd
pad will suffice as the biasing
inductor. Ensure the correct bond
length as shown in the assembly
diagrams.
CENTELLAX
• Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
UATM30M2C Datasheet
CENTELLAX
Chip size: 2390x920um (94.1x36.2mil)
Chip size tolerance: ±5um (0.2mil)
Chip thickness: 100 ±10um (4 ±0.4mil)
Pad dimensions: 80x80um (3.1x3.1mil)
Die size, pad locations, and pad descriptions
Applications Support
Alternate assembly diagrams and other additional
application support are available upon request.
Visit the Centellax website for large printable
assembly diagrams and application notes:
http://www.centellax.com/products/microwave/mmi
cs/UATM30M2C.shtml.
Pick-up and Chip Handling:
This MMIC has exposed air bridges on the top sur-
face.
Do not pick up chip with vacuum on the
die center;
handle from edges or with a custom
collet.
Thermal Heat Sinking:
2 - 30GHz bonding diagram
To avoid damage and for optimum performance,
you must observe the maximum channel tempera-
ture and ensure adequate heat sinking.
ESD Handling and Bonding:
This MMIC is ESD sensitive;
preventive meas-
ures should be taken during handling, die attach,
and bonding.
Epoxy die attach is recommended.
Please visit
our website for more handling, die attach and bond-
ing information: http://www.centellax.com/.
Recommended Components
>20pF DC Block:
Presidio SL1010X7R101M16VH
>120pF DC Block:
Presidio SL1010X7R181M16VH
Drain Bias Inductor:
Piconics CC21T36K240G5
Bypass Capacitors:
Drain: Presidio SL5050X7R222M16VH
Gate: Presidio SL3535X7R182M16VH
40MHz - 30GHz bonding diagram
CENTELLAX
• Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. Copyright © 2001-2006 Centellax, Inc. Printed in USA. 19 Apr 2006.
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