74HC237-Q100
3-to-8 line decoder, demultiplexer with address latches
Rev. 1 — 14 January 2013
Product data sheet
1. General description
The 74HC237-Q100 is a 3-to-8 line decoder, demultiplexer with latches at the three
address inputs (An). The 74HC237-Q100 essentially combines the 3-to-8 decoder
function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the
74HC237-Q100 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes
from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in
the latches. Further address changes are ignored as long as LE remains HIGH. The
output enable input (E1 and E2) controls the state of the outputs independent of the
address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The 74HC237-Q100 is ideally suited for implementing non-overlapping decoders in
3-state systems and strobed (stored address) applications in bus-oriented systems.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent controls
Active HIGH mutually exclusive outputs
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC237D-Q100
40 C
to +125
C
Name
SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Type number
Nexperia
74HC237-Q100
3-to-8 line decoder, demultiplexer with address latches
4. Functional diagram
4
LE
Y0 15
Y1 14
1 A0
2 A1
3 A2
INPUT
LATCHES
3 TO 8
DECODER
Y2 13
Y3 12
Y4 11
Y5 10
Y6 9
Y7 7
5 E1
6 E2
001aab871
Fig 1.
Functional diagram
DX
4
1
2
3
2
C8
0
8D,G
0
7
0
1
2
3
4
5
5
4
LE
Y0
Y1
1
2
3
A0
A1
A2
INPUT
LATCHES
Y2
Y3
3 TO 8
DECODER Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
5
E1
5
6
E2
001aab869
15
14
13
12
11
10
9
7
&
6
7
6
X/Y
4
1
2
3
C8
8D,1
8D,2
8D,4
0
1
2
3
4
5
&
6
7
EN
001aab870
15
14
13
12
11
10
9
7
6
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC237_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 14 January 2013
2 of 16
Nexperia
74HC237-Q100
3-to-8 line decoder, demultiplexer with address latches
A0
A0
LE
LATCH
A0
LE
Y0
Y1
A1
A1
LE
LATCH
A1
LE
Y2
A2
A2
LE
LATCH
A2
LE
Y3
Y4
LE
Y5
Y6
Y7
E1
001aab872
E2
Fig 4.
Logic diagram
74HC237_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 14 January 2013
3 of 16
Nexperia
74HC237-Q100
3-to-8 line decoder, demultiplexer with address latches
5. Pinning information
5.1 Pinning
+&4
$
$
$
/(
(
(
<
*1'
DDD
9
&&
<
<
<
<
<
<
<
Fig 5.
Pin configuration SO16
5.2 Pin description
Table 2.
Symbol
A0 to A2
LE
E1
E2
Y0 to Y7
GND
V
CC
Pin description
Pin
1, 2, 3
4
5
6
8
16
Description
data input
latch enable input (active LOW)
data enable input 1 (active LOW)
data enable input 2 (active HIGH)
ground (0 V)
supply voltage
15, 14, 13, 12, 11, 10, 9, 7 output
74HC237_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 14 January 2013
4 of 16
Nexperia
74HC237-Q100
3-to-8 line decoder, demultiplexer with address latches
6. Functional description
Table 3.
Enable
LE
H
X
X
L
L
L
L
L
L
L
L
[1]
Function table
Input
E1
L
H
X
L
L
L
L
L
L
L
L
E2
H
X
L
H
H
H
H
H
H
H
H
A0
X
X
X
L
H
L
H
L
H
L
H
A1
X
X
X
L
L
H
H
L
L
H
H
A2
X
X
X
L
L
L
L
H
H
H
H
Output
Y0
stable
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
[1]
Max
+7
20
20
25
+50
50
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
V
I
V
O
T
amb
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Conditions
Min
2.0
0
0
40
Typ
5.0
-
-
+25
Max
6.0
V
CC
V
CC
+125
Unit
V
V
V
C
74HC237_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 14 January 2013
5 of 16
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