S i 5 3 5 0 C- B
F
ACTORY
- P
ROGRAMMABLE
A
NY
- F
REQUENCY
CMOS
C
L O C K
G
ENERATOR
+ PLL
Features
www.silabs.com/custom-timing
Generates up to 8 non-integer-related
frequencies from 2.5 kHz to 200 MHz
Exact frequency synthesis at each
output (0 ppm error)
Glitchless frequency changes
Low output period jitter: < 70 ps pp, typ
Configurable Spread Spectrum
selectable at each output
User-configurable control pins:
Output Enable (OEB_0/1/2)
Power Down (PDN)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)
Loss of Lock Status (LOLB)
Supports static phase offset
Rise/fall time control
Operates from a low-cost, fixed
frequency crystal: 25 or 27 MHz
Separate voltage supply pins provide
level translation:
Core VDD: 1.8V, 2.5 V or 3.3 V
Output VDDO: 1.8 V, 2.5 V, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption (25 mA
core, typ)
Available in 2 packages types:
10-MSOP: 3 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
10-MSOP
20-QFN
Applications
Ordering Information:
See Page 18
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Handheld instrumentation
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
The Si5350C generates free-running and/or synchronized clocks selectable on each
of its outputs. A dual PLL + high resolution MultiSynth
TM
fractional divider
architecture enables this user-definable custom timing device to generate any of the
specified output frequencies at any of its outputs. This allows the Si5350C to replace
a combination of crystals, crystal oscillators, and synchronized clocks (PLL). Custom
pin-controlled Si5350C devices can be requested using the ClockBuilder web-based
part number utility (www.silabs.com/ClockBuilder).
Functional Block Diagram
Rev. 1.1 9/18
Copyright © 2018 by Silicon Laboratories
Si5350C-B
Si5350C-B
Table 1. The Complete Si5350/51 Clock Generator Family
Part Number
Si5351A-B-GT
Si5351A-B-GM
Si5351B-B-GM
Si5351C-B-GM
Si5351A-Bxxxxx-GT
Si5351A-Bxxxxx-GM
Si5351B-Bxxxxx-GM
Si5351C-Bxxxxx-GM
Si5350A-Bxxxxx-GT
Si5350A-Bxxxxx-GM
Si5350B-Bxxxxx-GT
Si5350B-Bxxxxx-GM
Si5350C-Bxxxxx-GT
Si5350C-Bxxxxx-GM
I2C or Pin
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
Pin
Pin
Pin
Pin
Pin
Pin
Frequency Reference
XTAL only
XTAL only
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL only
XTAL only
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL only
XTAL only
XTAL and/or Voltage
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL and/or CLKIN
Programmed?
Blank
Blank
Blank
Blank
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Outputs
3
8
8
8
3
8
8
8
3
8
3
8
3
8
Datasheet
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5350A-B
Si5350A-B
Si5350B-B
Si5350B-B
Si5350C-B
Si5350C-B
Notes:
1.
XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.
2.
Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.
2
Rev. 1.1
Si5350C-B
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si5350C Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Configuring the Si5350C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. External Clock Input Pin (CLKIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4. Programmable Control Pins (P0–P3) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2. 10-pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1. 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.2. 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9. 10-pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
10. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
11.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Rev. 1.1
3
Si5350C-B
1. Electrical Specifications
Table 2. Recommended Operating Conditions
Parameter
Ambient Temperature
Symbol
T
A
V
DD
Test Condition
Min
–40
1.71
Core Supply Voltage
2.25
3.0
1.71
Output Buffer Voltage
V
DDOx
2.25
3.0
Typ
25
1.8
2.5
3.3
1.8
2.5
3.3
Max
85
1.89
2.75
3.60
1.89
2.75
3.60
Unit
°C
V
V
V
V
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD
and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all
VDDOx be powered up either before or at the same time as VDD.
Table 3. DC Characteristics
(V
DD
= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Symbol
Test Condition
Enabled 3 outputs
Min
—
—
—
—
—
—
—
Typ
20
25
—
2.2
Max
35
45
50
5.6
Unit
mA
mA
µA
mA
µA
µA
Core Supply Current*
I
DD
Enabled 8 outputs
Power Down (PDN = V
DD
)
Output Buffer Supply
Current (Per Output)*
I
DDOx
I
P1-P3
I
P0
C
L
= 5 pF
Pins P1, P2, P3
V
P1-P3
< 3.6 V
Pin P0
3.3 V VDDO, default high
drive.
—
—
50
10
30
—
Input Current
Output Impedance
Z
OI
*Note:
Output clocks less than or equal to 100 MHz.
4
Rev. 1.1
Si5350C-B
Table 4. AC Characteristics
(V
DD
= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Power-Up Time
Powerup Time, PLL Bypass
Mode
Output Enable Time
Output Frequency Transition
Time
Spread Spectrum Frequency
Deviation
Spread Spectrum
Modulation Rate
Symbol
T
RDY
Test Condition
From V
DD
= V
DDmin
to valid
output clock, C
L
= 5 pF,
f
CLKn
> 1 MHz
From V
DD
= V
DDmin
to valid
output clock, C
L
= 5 pF,
f
CLKn
> 1 MHz
From OEB assertion to valid
clock output, C
L
= 5 pF, f
CLKn
> 1 MHz
f
CLKn
> 1 MHz
Down Spread
Selectable in 0.1% steps
Min
—
Typ
2
Max
10
Unit
ms
T
BYP
—
0.5
1
ms
T
OE
T
FREQ
SS
DEV
SS
MOD_C
—
—
–0.1
30
—
—
—
31.5
10
10
–2.5
33
µs
µs
%
kHz
Table 5. Input Characteristics
(V
DD
= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Crystal Frequency
P0-P3 Input Low Voltage
P0-P3 Input High Voltage
CLKIN Frequency Range
CLKIN Input Low Voltage
CLKIN Input High Voltage
Symbol
f
XTAL
V
IL_P0-3
V
IH_P0-3
f
CLKIN
V
IL_CLKIN
V
IH_CLKIN
Test Condition
Min
25
–0.1
Typ
—
—
—
—
—
—
—
Max
27
0.3 x V
DD
3.60
3.60
100
0.3 x V
DD
3.60
Units
MHz
V
V
V
MHz
V
V
V
DD
= 2.5 V or 3.3 V
V
DD
= 1.8 V
0.7 x V
DD
0.8 x V
DD
10
–0.1
0.7 x V
DD
Rev. 1.1
5
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