NCP81158D
Synchronous Buck MOSFET
Driver
The NCP81158D is a high−performance dual MOSFET gate driver
in a small 3 mm x 3 mm package, optimized to drive the gates of both
high−side and low−side power MOSFETs in a synchronous buck
converter. The driver outputs can be placed into a high−impedance
state via the tri−state PWM and EN inputs. The NCP81158D comes
packaged with an integrated boost diode to minimize external
components. A VCC UVLO function guarantees the outputs are low
when the supply voltage is low.
Features
1
DFN8
CASE 506BJ
1158D
A
L
Y
W
G
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MARKING
DIAGRAM
1
1158D
ALYWG
G
8
•
•
•
•
•
•
•
When Device is Powered, Fast PWM Response to EN Going High
Space−efficient 3 mm x 3 mm DFN8 Thermally−Enhanced Package
VCC Range of 4.5 V to 5.5 V
Internal Bootstrap Diode
5 V 3−stage PWM Input
Diode Braking Capability via EN Mid−state
Adaptive Anti−cross Conduction Circuit Protects Against
Cross−conduction during FET Turn−on and Turn−off
•
Output Disable Control Turns Off Both MOSFETs via Enable Pin
•
VCC Undervoltage Lockout
•
These Devices are Pb−free, Halogen−free/BFR−free and are RoHS
Compliant
Typical Applications
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT DIAGRAM
BST
PWM
EN
VCC
1
2
3
4
8
7
6
5
DRVH
SW
GND
DRVL
•
Power Solutions for Notebook and Desktop Systems
FLAG
9
ORDERING INFORMATION
Device
NCP81158DMNTXG
Package
DFN8
(Pb−Free)
Shipping
†
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2017
1
April, 2017 − Rev. 1
Publication Order Number:
NCP81158D/D
NCP81158D
BST
VCC
ZCD
Auto−
cal
Logic
PWM
Anti−
Cross
Conduction
VCC
DRVL
SW
DRVH
EN
ZCD
Detection
UVLO
VCC
GND
Figure 1. Block Diagram
PIN DESCRIPTIONS
Pin No.
1
2
3
Symbol
BST
PWM
EN
Description
Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and
the SW pin.
Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode
Emulation Enabled, High = High Side FET Enabled.
Logic input. A logic high to enable the part and a logic low to disable the part. Three states logic input:
EN = High to enable the gate driver;
EN = Low to disable the driver;
EN = Mid to go into diode mode (both high and low side gate drive signals are low)
Power supply input. Connect a bypass capacitor (0.1
mF)
from this pin to ground.
Low side gate drive output. Connect to the gate of low side MOSFET.
Bias and reference ground. All signals are referenced to this node.
Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET.
High side gate drive output. Connect to the gate of high side MOSFET.
Thermal flag. There is no electrical connection to the IC. Connect to ground plane.
4
5
6
7
8
9
VCC
DRVL
GND
SW
DRVH
FLAG
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2
NCP81158D
APPLICATION CIRCUIT
5V_POWER
R2
0.0
R1
0.0
C2
0.1 uF
NCP81158D
R3
BST
DRVH
VIN
Q1
C4
4.7 uF
C5
4.7 uF
C6
C7
4.7 uF 390 uF
L
R4
2.2
C3
2700 pF
235 nH
VCCP
0.0
PWM
DRON
PWM
SW
EN
GND
Q2
Q3
VCC
DRVL
C1
1 uF
PAD
Figure 2. Application Circuit
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NCP81158D
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Symbol
V
CC
BST
Pin Name
Main Supply Voltage Input
Bootstrap Supply Voltage
V
MAX
6.5 V
7.5 V < 80 ns
35 V wrt/ GND
40 V
v
50 ns wrt/ GND
6.5 V wrt/ SW
7.7 V < 50 ns wrt/ SW
35 V
40 V
v
80 ns
BST + 0.3 V
SW + 7 V (< 80 ns)
V
CC
+ 0.3 V
7 V (< 80 ns)
6.5 V
6.5 V
0V
V
MIN
−0.3 V
−0.3 V wrt/SW
SW
DRVH
DRVL
PWM
EN
GND
Switching Node (Bootstrap Supply Return)
High Side Driver Output
Low Side Driver Output
DRVH and DRVL Control Input
Enable Pin
Ground
−5 V
−10 V (200 ns)
−0.3 V wrt/SW
−2 V (< 200 ns) wrt/SW
−0.3 V DC
−5 V (< 200 ns)
−0.3 V
−0.3 V
0V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to AGND unless noted otherwise.
THERMAL INFORMATION
Symbol
R
qJA
T
J
T
A
T
STG
MSL
Parameter
Thermal Characteristic QFN Package (Note 1)
Operating Junction Temperature Range (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Moisture Sensitivity Level − QFN Package
Value
119
−40 to 150
−40 to +100
−55 to +150
1
Unit
°C/W
°C
°C
°C
*The maximum package power dissipation must be observed.
1. 1 in
2
Cu, 1 oz. thickness.
2. JESD 51−7 (1S2P Direct−Attach Method) with 1 LFM.
NCP81158D ELECTRICAL CHARACTERISTICS
(−40°C < T
A
< +100°C; 4.5 V < V
CC
< 5.5 V, 4.5 V < BST−SWN < 5.5 V,
4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted)
Parameter
SUPPLY VOLTAGE
VCC Operation Voltage
UNDERVOLTAGE LOCKOUT
VCC Start Threshold
VCC UVLO Hysteresis
SUPPLY CURRENT
Shutdown Mode
Normal Mode
Standby Current
Standby Current
BOOTSTRAP DIODE
Forward Voltage
V
CC
= 5 V, forward bias current = 2 mA
0.1
0.4
0.6
V
I
CC
+ I
BST
, EN = GND
I
CC
+ I
BST
, EN = 5 V, PWM = OSC
I
CC
+ I
BST
, EN = HIGH, PWM = LOW,
No loading on DRVH & DRVL
I
CC
+ I
BST
, EN = HIGH, PWM = HIGH,
No loading on DRVH & DRVL
690
4.7
0.9
1.1
900
mA
mA
mA
mA
3.8
150
4.35
200
4.5
250
V
mV
4.5
5.5
V
Test Conditions
Min
Typ
Max
Unit
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4
NCP81158D
NCP81158D ELECTRICAL CHARACTERISTICS
(−40°C < T
A
< +100°C; 4.5 V < V
CC
< 5.5 V, 4.5 V < BST−SWN < 5.5 V,
4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted)
Parameter
PWM INPUT
PWM Input High
PWM Mid−State
PWM Input Low
ZCD Blanking Timer
HIGH SIDE DRIVER
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVH Rise Time tr
DRVH
DRVH Fall Time tf
DRVH
DRVH Turn−Off Propagation Delay tpdl
DRVH
DRVH Turn−On Propagation Delay tpdh
DRVH
SW Pulldown Resistance
DRVH Pulldown Resistance
LOW SIDE DRIVER
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVL Rise Time tr
DRVL
DRVL Fall Time tf
DRVL
DRVL Turn−Off Propagation Delay tpdl
DRVL
DRVL Turn−On Propagation Delay tpdh
DRVL
DRVL Pulldown Resistance
EN INPUT
Input Voltage High
Input Voltage Mid
Input Voltage Low
Input bias current
Propagation Delay Time, Falling
Propagation Delay Time, Rising
SW NODE
SW Node Leakage Current
Zero Cross Detection Threshold Voltage
−6.0
20
mA
mV
EN falling past 0.6V to DRVL @ 90%, PWM = 0V
EN rising past 3.3V to DRVL @ 10%, PWM = 0V
−1.0
20
25
3.3
1.35
1.8
0.6
1.0
40
V
V
V
mA
ns
ns
CLOAD = 3 nF
CLOAD = 3 nF
CLOAD = 3 nF
CLOAD = 3 nF
DRVL to PGND, V
CC
= PGND
10
5.0
45
0.9
0.4
16
11
1.7
0.8
25
15
30
25
W
W
ns
ns
ns
ns
kW
V
BST
−V
SW
= 5 V
V
BST
−V
SW
= 5 V
V
CC
= 5 V, 3 nF load, V
BST
−V
SW
= 5 V
V
CC
= 5 V, 3 nF load, V
BST
−V
SW
=5 V
CLOAD = 3 nF
CLOAD = 3 nF
SW to PGND
DRVH to SW, BST−SW = 0 V
10
10
45
45
0.9
0.7
16
11
1.7
1.7
25
18
30
40
W
W
ns
ns
ns
ns
kW
kW
350
3.4
1.3
2.7
0.7
V
V
V
ns
Test Conditions
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 1. DECODER TRUTH TABLE
Input
PWM High (Enable High)
PWM Mid (Enable High)
PWM Mid (Enable High)
PWM Low (Enable High)
Enable at Mid
ZCD
ZCD Reset
Positive Current Through the Inductor
Zero Current Through the Inductor
ZCD Reset
X
DRVL
Low
High
Low
High
Low
DRVH
High
Low
Low
Low
Low
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