NCP12510
Current-Mode PWM
Controller for Off-line
Power Supplies
The NCP12510 is a highly integrated PWM controller capable of
delivering a rugged and high performance offline power supply in a
tiny TSOP−6 package. With a voltage supply range up to 35 V, the
controller hosts a jittered 65−kHz or 100−kHz switching circuitry
operated in peak current mode control. When the power on the
secondary side starts decreasing, the controller automatically folds
back its switching frequency down to a minimum level of 26 kHz. As
the power further goes down, the part enters skip cycle while limiting
the peak current.
Over Power Protection (OPP) is a difficult exercise especially when
no−load standby requirements drive the converter specifications. The
ON Semiconductor proprietary integrated OPP allows harness the
maximum delivered power without affecting the standby performance
simply via two external resistors. An Over Voltage Protection (OVP)
input is also combined on the same pin and protects the whole circuitry
in case of optocoupler destruction or adverse open loop operation.
Finally, a timer−based short−circuit protection offers the best
protection scheme, allowing precisely select the protection trip point
without caring of a loose coupling between the auxiliary and the power
windings.
NCP12510 is improved and pin compatible controller based on very
popular flyback controller NCP1250.
Features
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MARKING
DIAGRAM
TSOP−6
(SOT23−6)
SN SUFFIX
CASE 318G
STYLE 13
5Dx
x
A
Y
W
G
5DxAYWG
G
1
1
= Specific Device Code
= A, 2, C, J, or K
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
GND
FB
1
2
6
5
DRV
V
CC
•
Fixed−Frequency 65 kHz or 100 kHz Current−Mode Control
•
•
•
•
•
•
•
•
•
•
•
•
•
Operation
OPP/Latch 3
4 CS
Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load
(Top View)
Conditions
Frequency Jittering in Normal and Frequency Foldback Modes
Internal and Adjustable Over Power Protection (OPP) Circuit
ORDERING INFORMATION
Auto−Recovery Over Voltage Protection (OVP) on the VCC Pin
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
Internal and Adjustable Slope Compensation
Internal Fixed 4 ms Soft−Start
Auto−Recovery or Latched Short−Circuit Protection
•
EPS 2.0 Compliant
Pre−Short Ready for Latched OCP Version
•
This is a Pb−Free Device
OVP/OTP Latch Input for Improved Robustness
Typical Applications
+300 mA/ −500 mA Source/Sink Drive Capability
•
Ac−dc Converters for TVs, Set−top Boxes and DVD
Improved Consumption
Players
Improved Reset Time in Latch State
•
Offline Adapters for Notebooks and Netbooks
High Robustness and High ESD Capabilities
©
Semiconductor Components Industries, LLC, 2016
1
November, 2017 − Rev. 3
Publication Order Number:
NCP12510/D
NCP12510
Figure 1. Typical Application Example
Table 1. PIN DESCRIPTION
Pin No
1
2
3
Pin Name
GND
FB
OPP/Latch
Function
−
Feedback pin
Adjust the Over Power
Protection Latches off the part
Current sense + slope
compensation
Supplies the controller −
protects the IC
Driver output
The controller ground.
Hooking an optocoupler collector to this pin will allow regulation.
A resistive divider from the auxiliary winding to this pin sets the OPP
compensation level during the on−time. When the voltage exceeds a certain
level at turn off, the part is fully latched off.
This pin monitors the primary peak current but also offers a means to
introduce slope compensation.
This pin is connected to an external auxiliary voltage. When the V
CC
exceeds a
certain level, the part enters an auto−recovery hiccup.
The driver output to an external MOSFET gate.
Pin Description
4
5
6
CS
V
CC
DRV
Table 2. DEVICE OPTIONS AND ORDERING INFORMATION
Controller
(Note 1)
NCP12510ASN65T1G
NCP12510BSN65T1G
NCP12510CSN65T1G
NCP12510ASN100T1G
NCP12510BSN100T1G
Package
Marking
5DA
5D2
5DC
5DJ
5DK
OCP Protection
Latched
Auto−recovery
Auto−recovery
Latched
Auto−recovery
OVP/OTP
Protection
Latched
Latched
Auto−recovery
Latched
Latched
Switching
Frequency
65 kHz
65 kHz
65 kHz
100 kHz
100 kHz
TSOP−6
(Pb−Free)
3000 /
Tape & Reel
Package
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1. Other options available upon customer request.
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2
NCP12510
OPP/
Latch
V
OPP
DRV stop
Latch / Auto-
recovery mode
RST
t
latch(del)
Up Counter
to 4
OVP/OTP
Latch
t
latch(blank)
DRV pulse
+
Latch / Auto-revery
management
V
CC(OVP)
V
CC(min)
OVP/OTP
Latch
OCP Fault
Pre-short
Note: depend on IC
option
+
V
latch
Pre-short logic – available only for latched OCP version
Armed flag
V
CC(on)
1
st
DRV pulse
during IC start
S
R
IC in regulation
FB@gnd
V
CC(min)
Clamp
Q
Q
V
CC(OVP)
+
t
OVP(del)
_
+
V
OVP
R
ramp
V
FB(open)
+
V
skip
IC in regulation
R
eq
K
ratio
Up counter
to 8
RST
Error
flag
_
FB
peak current
freeze
Soft-start
V
OPP
+
V
limit
Figure 2. Internal Circuit Architecture
_
+
V
limit
+ V
OPP
+
CS
LEB
+
_
+
_
Jittering
IC start
IC stop
IC reset
Internal
supply
V
CC
and logic
management
Latch / Auto-
recovery mode
VCC
Pre-short
DRV pulse
DRV
pulse
65 / 100 kHz
Oscillator
D
max
S
R
Q
Q
Frequency
foldback
DRV
IC stop
DRV pulse
DRV stop
R
S
Q
Q
RST
Fault timer
OCP
Fault
GND
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NCP12510
Table 3. MAXIMUM RATINGS TABLE
Symbol
V
CC
V
DRV(tran)
V
CS
, V
FB
, V
OPP
V
OPP(tran)
I
source,max
I
sink,max
I
OPP
R
θJ−A
T
J,max
HBM
CDM
Rating
Power Supply voltage, VCC pin, continuous voltage
Maximum DRV pin voltage when DRV in H state, transient voltage (Note 1)
Maximum voltage on low power pins CS, FB and OPP (Note 2)
Maximum negative transient voltage on OPP pin (Note 2)
Maximum sourced current, pulsed width < 800 ns
Maximum sinked current, pulse width < 800 ns
Maximum injected negative current into the OPP pin (pin 3)
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Storage Temperature Range
Human Body Model ESD Capability per JEDEC JESD22−A114F (All pins)
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
Value
−0.3 to 35
−0.3 to V
CC
+ 0.3
−0.3 to 5.5
−1
0.6
1.0
−2
360
150
−60 to +150
4
750
Unit
V
V
V
V
A
A
mA
°C/W
°C
°C
kV
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns.
2. See the Figure 3 for detailed specification of transient voltage.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
on-time
0V
t
V
OPP
(t)
V
CS
V
FB
V
OPP
500 ns
Max current during
overshoot can 't
exceed 3 mA
7.5 V – Max transient
voltage
cycle-by-cycle
5.5 V – Max DC
voltage
V
OPP, max
V
OPP,max
= -0.75 V, T
j
= -25
°C
V
OPP,max
= -0.65 V, T
j
= 25
°C
V
OPP,max
= -0.3 V, T
j
= 125
°C
– Worst case
V
OPP
-1 V
500 ns
V
OPP
must stay between 0V and –0.3 V for
a linear OPP operation
SOA
0V
t
Figure 3. Negative Pulse for OPP Pin during On−time and Positive Pulse for All Low Power Pins
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4
NCP12510
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
= −40°C to +125°C, V
CC
= 12 V unless otherwise noted)
Symbol
SUPPLY SECTION
V
CC(on)
V
CC(min)
V
CC(hyst)
V
CC(reset)
V
CC(reset_
hyst)
Rating
Pin
Min
Typ
Max
Unit
V
CC
increasing level at which driving pulses are authorized
V
CC
decreasing level at which driving pulses are stopped
Hysteresis V
CC(on)
– V
CC(min)
Latched state reset voltage
Defined hysteresis between minimum and reset voltage V
CC(min)
–
V
CC(reset)
Defined hysteresis for hiccupping between two voltage levels in latch mode
Start−up current (V
CC(on)
– 100 mV)
Internal IC consumption with V
FB
= 3.2 V, f
SW
= 65 kHz and C
L
= 0 nF
Internal IC consumption with V
FB
= 3.2 V, f
SW
= 100 kHz and C
L
= 0 nF
Internal IC consumption with V
FB
= 3.2 V, f
SW
= 65 kHz and C
L
= 1 nF
Internal IC consumption with V
FB
= 3.2 V, f
SW
= 100 kHz and C
L
= 1 nF
Internal consumption in skip mode – non switching, V
FB
= 0 V
Internal consumption in fault mode – during going−down V
CC
cycle,
V
FB
= 4 V
Internal IC consumption in skip mode for 65 kHz version (V
CC
= 14 V,
driving a typical 7−A/600−V MOSFET, includes opto current) – (Note 4)
5
5
5
5
5
5
5
5
5
5
5
5
16
8.3
7.7
−
0.15
−
−
−
−
−
−
−
18
8.9
−
8.6
0.30
0.55
6
1.0
1.1
1.7
2.3
300
370
420
20
9.5
−
−
0.45
−
10
1.4
1.5
2.7
3.0
−
−
−
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
V
CC(latch_hyst)
I
CC1
I
CC2
I
CC3
I
CC(no−load)
I
CC(fault)
I
CC(standby)
DRIVE OUTPUT
t
r
t
f
R
OH
R
OL
I
source
I
sink
V
DRV(low)
V
DRV(high)
Output voltage rise−time @ C
L
= 1 nF, 10−90% of output signal
Output voltage fall−time @ C
L
= 1 nF, 10−90% of output signal
Source resistance, V
CC
= 12 V, I
DRV
= 100 mA
Sink resistance, V
CC
= 12 V, I
DRV
= 100 mA
Peak source current, V
GS
= 0 V
Peak sink current, V
GS
= 12 V
DRV pin level at V
CC
= V
CC(min)
+ 100 mV with a 33 kW resistor to GND
DRV pin level at V
CC
= V
OVP
– 100 mV (DRV unloaded)
6
6
6
6
6
6
6
6
−
−
−
−
−
−
8
10
40
30
28
7
300
500
−
12
−
−
−
−
−
−
−
14
ns
ns
W
W
mA
mA
V
V
CURRENT COMPARATOR
V
limit
V
CS(fold)
V
CS(freeze)
t
DEL
t
LEB
t
SS
I
OPPs
I
OPPo
I
OOPv
Maximum internal current set point – T
J
= 25°C – pin 3 grounded
Maximum internal current set point – T
J
= −40°C to 125°C – pin 3 grounded
Internal voltage setpoint for frequency foldback trip point – 59% of V
limit
Internal peak current setpoint freeze (≈31% of V
limit
)
Propagation delay from CS pin to DRV output
Leading Edge Blanking Duration
Internal soft−start duration activated upon startup or auto−recovery
Set point decrease for pin 3 grounded
Set point decrease for pin 3 biased to −250 mV
Voltage set point for pin 3 biased to −250 mV, T
J
= 25°C
Voltage set point for pin 3 biased to −250 mV, T
J
= −40° to 125°C
4
4
4
4
4
4
3
3
3
0.744
0.720
−
−
−
−
−
−
−
0.51
0.50
0.8
0.8
475
250
50
300
4
0
31.3
0.55
0.55
0.856
0.880
−
−
80
−
−
−
−
0.60
0.62
V
mV
mV
ns
ns
ms
%
%
V
INTERNAL OSCILLATOR
f
OSC(nom)
D
max
f
jitter
Oscillation frequency (65 kHz version)
Oscillation frequency (100 kHz version)
Maximum duty−ratio
Frequency jittering in percentage of f
OSC
– jitter is kept even in foldback
mode
−
−
−
61
92
76
−
65
100
80
±5
71
108
84
−
kHz
%
%
4. Application parameter for information only.
5. 1−MW resistor is connected from pin 4 to the ground for the measurement.
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