a
FEATURES
High Speed Version of SMP08
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
APPLICATIONS
Multiple Path Timing Deskew for A.T.E.
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
INPUT
3
Octal Sample-and-Hold
with Multiplexed Input
SMP18
FUNCTIONAL BLOCK DIAGRAM
(LSB)
A
11
(MSB)
C
9
B
10
INH
6
8 DGND
1 OF 8 DECODER
16 V
DD
SW
13 CH
0
OUT
SW
14 CH
1
OUT
SW
15 CH
2
OUT
SW
12 CH
3
OUT
SW
1
CH
4
OUT
SW
5
CH
5
OUT
GENERAL DESCRIPTION
The SMP18 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP18 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±
1/2 LSB in less than 2.5 microseconds. The SMP18’s output
swing includes the negative supply in both single and dual sup-
ply operation.
The SMP18 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP18 ideal for
calibration requirements that have previously required an ASIC,
or high cost multiple D/A converters.
The SMP18 is also ideally suited for a wide variety of sample-
and-hold applications including amplifier offset or VCA gain ad-
justments. One or more SMP18s can be used with single or
multiple DACs to provide multiple set points within a system.
SW
2
CH
6
OUT
SW
HOLD CAPS
(INTERNAL)
4 CH
7
OUT
7 V
SS
SMP18
The SMP18 offers significant cost and size reduction over
discrete designs. It is available in a 16-pin plastic DIP, a
narrow body SO-16 surface-mount SOIC package or the thin
TSSOP-16 package. The SMP18 is a higher speed direct
replacement for the SMP08.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
ELECTRICAL CHARACTERISTICS
P
arameter
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
2
Acquisition Time
3
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
Capacitive Load Stability
Analog Crosstalk
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Symbol
V
OS
V
HS
∆V
CH
/∆t
I
SOURCE
I
SINK
SMP18–SPECIFICATIONS
(@ V
= +5 V, V
SS
= –5 V, DGND = 0 V, R
L
= No Load, T
A
= –40 C to +85 C for SMP18F,
unless otherwise noted)
DD
Conditions
–3 V
≤
V
IN
≤
+3 V
T
A
= +25°C, V
IN
= 0 V
–40°C
≤
T
A
≤
+85°C, V
IN
= 0 V
V
IN
= 0 V, T
A
= +25°C to +85°C
V
IN
= 0 V, T
A
= –40°C
T
A
= +25°C, V
IN
= 0 V
V
IN
= 0 V
1
V
IN
= 0 V
1
R
L
= 20 kΩ
Min
Typ
0.01
2.5
3.5
4
2
Max
10
20
6
8
40
+3.0
Units
%
mV
mV
mV
mV
mV/s
mA
mA
V
V
V
µA
µs
µs
ns
ns
ns
V/µs
pF
dB
dB
mA
1.2
0.5
–3.0
2.4
V
INH
V
INL
I
IN
t
AQ
t
H
t
CH
t
DCS
t
IR
SR
V
IN
= 2.4 V
T
A
= +25°C, –3 V to +3 V to 0.1%
To
±
1 mV of Final Value
0.5
3.5
1
90
45
90
6
500
–72
60
75
5.5
0.8
1
<30% Overshoot
–3 V to +3 V Step
PSRR
I
DD
V
SS
=
±
5 V to
±
6 V
T
A
= +25°C
–40°C
≤
T
A
≤
+85°C
7.5
7.5
9.5
mA
ELECTRICAL CHARACTERISTICS
Parameter
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
Symbol
V
OS
V
HS
∆V
CH
/∆t
I
SOURCE
I
SINK
(@ V
DD
= +12 V, V
SS
= 0 V, DGND = 0 V, R
L
= No Load, T
A
= –40 C to +85 C for SMP18F,
unless otherwise noted)
Conditions
60 mV
≤
V
IN
≤
10 V
T
A
= +25°C, V
IN
= 6 V
–40°C
≤
T
A
≤
+85°C, V
IN
= 6 V
V
IN
= 6 V, T
A
= +25°C to +85°C
V
IN
= 6 V, T
A
= –40°C
T
A
= +25°C, V
IN
= 6 V
V
IN
= 6 V
1
V
IN
= 6 V
1
R
L
= 20 kΩ
R
L
= 10 kΩ
Min
Typ
0.01
2.5
3.5
4
2
1.2
0.5
0.06
0.06
Max
10
20
6
8
40
10.0
9.5
Limits
%
mV
mV
mV
mV
mV/s
mA
mA
V
V
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
2
Acquisition Time
3
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
4
Capacitive Load Stability
Analog Crosstalk
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
V
INH
V
INL
I
IN
t
AQ
t
H
t
CH
t
DCS
t
IR
SR
2.4
V
IN
= 2.4 V
T
A
= +25°C, 0 to 10 V to 0.1%
To
±
1 mV of Final Value
0.5
2.5
1
90
45
90
7
500
–72
60
75
6.0
8.0
0.8
1
3.25
V
V
µA
µs
µs
ns
ns
ns
V/µs
pF
dB
dB
mA
mA
<30% Overshoot
0 V to 10 V Step
PSRR
I
DD
10.8 V
≤
V
DD
≤
13.2 V
T
A
= +25°C
–40°C
≤
T
A
≤
+85°C
8.0
10.0
NOTES
1
Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels.
2
All input control signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3
This parameter is guaranteed without test.
4
Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%.
Specifications subject to change without notice.
–2–
REV. C
SMP18
ABSOLUTE MAXIMUM RATINGS
PIN CONNECTIONS
CH
4
OUT 1
CH
6
OUT 2
INPUT 3
CH
7
OUT 4
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
LOGIC
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
V
IN
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
V
OUT
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
(Not short-circuit protected)
Operating Temperature Range
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Package Type
16-Pin Plastic DIP (P)
16-Pin SOIC (S)
16-Lead TSSOP (RU)
JA
*
JC
16 V
DD
15 CH
2
OUT
14 CH
1
OUT
13 CH
0
OUT
TOP VIEW
CH
5
OUT 5 (Not to Scale) 12 CH
3
OUT
INH 6
V
SS
7
DGND 8
11 A CONTROL
10 B CONTROL
9 C CONTROL
SMP18
Units
°C/W
°C/W
°C/W
Model
SMP18FP
SMP18FRU
SMP18FS
ORDERING GUIDE
76
92
180
33
27
35
NOTES
*θ
JA
is specified for worst case mounting conditions, i.e.,
θ
JA
is specified for device
in socket for plastic DIP packages;
θ
JA
is specified for device soldered to printed
circuit board for SOIC and TSSOP packages.
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Description
Plastic DIP
TSSOP-16
SO-16
Package
Option
N-16
RU-16
R-16A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP18 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
SMP18 –Typical Performance Characteristics
100
V
DD
= +12V
V
SS
= 0V
5
130
110
DROOP RATE – mV/s
V
DD
= +12V
V
SS
= 0V
T
A
= +85
°
C
NO LOAD
90
DROOP RATE – mV/s
DROOP RATE – mV/s
10
V
I N
= +6V
R
L
= 10kΩ
3
1
0
70
–1
V
DD
= +12V
V
SS
= 0V
T
A
= +25
°
C
NO LOAD
50
0.1
–3
30
0.01
–40
–20
0
20
40
60
80
100
–5
0
1
2
3
4
5
6 7
8
INPUT VOLTAGE – Volts
9
10
10
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
TEMPERATURE –
°
C
Droop Rate vs. Temperature
Droop Rate vs. Input Voltage
Droop Rate vs. Input Voltage
0
–1
HOLD STEP – mV
V
DD
= +12V
V
SS
= 0V
T
A
= +25
°
C
HOLD STEP – mV
1
0
–1
–2
–3
–4
–5
V
DD
= +12V
V
SS
= 0V
30
25
SLEW RATE – V/µs
V
DD
= +12V
V
SS
= 0V
T
A
= +25
°
C
NO LOAD
NO LOAD
–2
V
IN
= 6V
NO LOAD
20
+SR
15
–3
–4
10
–SR
–5
–6
–7
–55 –35 –15
5
–6
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
5
25
45
65
85 105 125
TEMPERATURE –
°
C
0
10
11
12
13
14
15
V
DD
– Volts
16
17
18
Hold Step vs. Input Voltage
Hold Step vs. Temperature
Slew Rate vs. V
DD
4
2
OFFSET VOLTAGE – mV
0
–2
–4
–6
–8
–10
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
R
L
= 20kΩ
R
L
= 10kΩ
R
L
=
V
DD
= +12V
V
SS
= 0V
OFFSET VOLTAGE – mV
20
15
10
5
R
L
=
0
–5
–10
–15
–20
0
1
2
R
L
= 10kΩ
V
DD
= +12V
V
SS
= 0V
OFFSET VOLTAGE – mV
T
A
= +85
°
C
4
2
0
–2
–4
–6
–8
–10
R
L
= 10kΩ
R
L
=
V
DD
= +12V
V
SS
= 0V
T
A
= –40
°
C
∞
T
A
= +25
°
C
∞
R
L
= 20kΩ
∞
R
L
= 20kΩ
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
Offset Voltage vs. Input Voltage
Offset Voltage vs. Input Voltage
Offset Voltage vs. Input Voltage
–4–
REV. C
Typical Performance Characteristics–SMP18
0
–1
V
DD
= +12V
V
SS
= 0V
14
12
V
SS
= 0V
NO LOAD
90
80
REJECTION RATIO – dB
70
60
50
40
30
20
10
14
16
18
V
DD
= +12V
V
SS
= 0V
+PSRR
V
IN
= +6V
T
A
= +25
°
C
NO LOAD
–PSRR
OFFSET VOLTAGE – mV
–2
–3
–4
–5
–6
–7
–8
–55 –35 –15
SUPPLY CURRENT – mA
V
I N
= +5V
R
L
= 10kΩ
10
+85
°
C
8
+25
°
C
6
–40
°
C
4
2
5
25
45
65
85 105 125
4
6
8
12
V
DD
– Volts
10
TEMPERATURE –
°
C
0
10
100
1k
10k
100k
FREQUENCY – Hz
1M
Offset Voltage vs. Temperature
Supply Current vs. V
DD
Sample Mode Power Supply Rejection
2
1
0
GAIN – dB
V
DD
= +6V
V
SS
= –6V
T
A
= +25
°
C
NO LOAD
90
45
PHASE SHIFT – Degrees
35
30
V
DD
= +12V
V
SS
= 0V
T
A
= +25
°
C
NO LOAD
0
–45
OUTPUT IMPEDANCE –
Ω
25
20
15
10
5
0
10
–1
PHASE
–2
–3
–4
–5
100
GAIN
–90
–135
–180
–225
10M
1k
10k
100k
FREQUENCY – Hz
1M
100
1k
10k
100k
FREQUENCY – Hz
1M
Gain, Phase Shift vs. Frequency
Output Impedance vs. Frequency
15
PEAK-TO-PEAK OUTPUT – Volts
V
DD
= +6V
V
SS
= –6V
T
A
= +25
°
C
NO LOAD
REJECTION RATIO – dB
60
50
+PSRR
40
V
DD
= +12V
30 V
SS
= 0V
T
A
= +25
°
C
20 NO LOAD
10 HOLD CAPACITORS
REFERENCED TO V
SS
0
–PSRR
12
9
6
3
0
10k
100k
1M
FREQUENCY – Hz
10M
–10
10
100
1k
10k
100k
FREQUENCY – Hz
1M
Maximum Output Voltage vs.
Frequency
Hold Mode Power Supply Rejection
REV. C
–5–
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