NCL30030
Combination Power Factor
Correction and
Quasi-Resonant Flyback
Controllers for LED Lighting
This combination IC integrates power factor correction (PFC) and
quasi−resonant flyback functionality necessary to implement a
compact and highly efficient LED driver for high performance LED
lighting applications.
The PFC stage utilizes a proprietary multiplier architecture to
achieve low harmonic distortion and near−unity power factor while
operating in a Critical Conduction Mode (CrM). The circuit
incorporates all the features necessary for building a robust and
compact PFC stage while minimizing the number of external
components.
The quasi−resonant current−mode flyback stage features a
proprietary valley−lockout circuitry, ensuring stable valley switching.
This system works down to the 4
th
valley and toggles to a frequency
foldback mode with a minimum frequency clamp beyond the 4
th
valley to eliminate audible noise. Skip mode operation allows
excellent efficiency in light load conditions while consuming very low
standby power consumption.
Common General Features
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SOIC−16 NB MISSING PIN 2
CASE 751DT
MARKING DIAGRAM
BO/HV
MULT
PControl
PONOFF
QCT
Fault
QFB
1
NCL30030xy
AWLYWWG
16
PFB
GND
PCS/PZCD
PDRV
QDRV
QCS
VCC
QZCD
•
Wide V
CC
Range from 9 V to 30 V with Built−in Overvoltage
•
•
•
•
•
Protection
High−Voltage Startup Circuit
Integrated High−Voltage Brown−Out Detector
Fault Input for Severe Fault Conditions, NTC Compatible (Latch and
Auto−Recovery Options)
0.5 A / 0.8 A Source / Sink Gate Drivers
Internal Temperature Shutdown
NCL30030 = Specific Device Code
x
= A or B
y
= 1, 2 or 3
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 31 of
this data sheet.
PFC Controller Features
•
Critical Conduction Mode with a Multiplier
•
Accurate Overvoltage Protection
•
Optional Bi−Level Line−Dependent Output Voltage
•
•
•
•
(2:1 / 1.77:1 Versions)
Fast Line / Load Transient Compensation
Boost Diode Short−Circuit Protection
Feed−Forward for Improved Operation across Line and
Load
Adjustable PFC Disable Threshold Based on Output
Power
•
Minimum Frequency Clamp Eliminates Audible Noise
•
Timer−Based Overload Protection (Latched or
•
•
•
•
•
•
•
•
•
•
Auto−Recovery options)
Adjustable Overpower Protection
Winding and Output Diode Short−Circuit Protection
4 ms Soft−Start Timer
These are Pb−Free Devices
High Power LED Drivers
Commercial LED ballasts
LED Signage Power Supplies
Adapters
Open Frame Power Supplies
LED Electronic Control Gear
Typical Applications
QR Flyback Controller Features
•
Valley Switching Operation with Valley−Lockout for
Noise−Free Operation
•
Frequency Foldback with Minimum Frequency Clamp
for Highest Performance in Standby Mode
©
Semiconductor Components Industries, LLC, 2015
1
March, 2015 − Rev. 1
Publication Order Number:
NCL30030/D
PDRV
VZCD
VCC
(Aux)
PCS/PZCD
PDRV
QCS
VCC
QCS
PCS/PZCD
U1
BO/HV
NCL30030
Figure 1. NCL30030 Typical Application Circuit
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PFB
GND
MULT PCS/PZCD
PDRV
PControl
QDRV
PONOFF
QCT
QCS
VCC
Fault
QFB
QZCD
NCL30030
2
VZCD
NCL30030
PUVP
+
PFB
16
K
POVP(xL)
D
POVP(xL)
−
V
PFB(disable)
V
PFB(HYS)
Latch
Auto−recovery
VCC(reset)
Central
POVP
Brownout
Low/High Line
VCC_OK
Logic
QR_EN
Reset
Low/High Line
Brownout
V
BO_BUF
VCC_OK
High Voltage
Startups
Detection, and
Logic
1
BO/HV
PFC
OVP
Detection
VCCOVP
VCC_OK
VCC(reset)
V DD
VCC
Management
I start1/2
10
VCC
C
CC
I
PControl(boost)
K
LOW
K
LOW(HYS)
I
EA
+
QR_EN
Soft−start
V
QILIM1
V
QFB
In Regulation
QZCD
Soft−start
V
PREF(xL)
−
PControl
4
V
PCONTROL(MAX)
V
CONTROL
V
PCONTROL(MIN)
PUVP
Disable PFC
t
Pdisable
I PONOFF
5
+
POVP
PUVP
PSKIP
PILIM1
PILIM2
V
PONHYS
−
V
POFF
PONOFF
Disable PFC
Low/High Line
R
t
on1x
R
Q
Dominant
Reset
Latch
Q
S
QRDRV
Q
Dominant
Reset
Latch
Q
S
PFCDRV
t Q(toutx)
12
QDRV
PSKIP
+
DV
PSKIP
−
In Regulation
Soft−start
V
QZCD
QZCD
V
PCONTROL
Low/High Line
V
BO_BUF
MULT
3
Multiplier
Valley
ZCD
Detect
9
V
QZCD(hys)
t delay(QSKIP)
QSkip
V
QZCD(th)
CT
Setpoint
Minimum
Frequency
LEB1
PILIM1
+
V
PILIM1
−
t
PFC(offx)
Timer
Oscillator
VCO
QRDRV
V
QFB
VCO
QRDRV
PILIM2
PFCDRV
ZCD
Detect
I PCS/PZCD
+
−
V
PZCD
PZCD
QSkip
Valley
t onQR(MAX)
QSkip
VCO
Valley
Select
Logic
I
QFB
V
QFB
/K
QFB
PCS/PZCD
14
LEB2
V
PILIM2
+
−
PDRV
13
PFCDRV
TSD
QOVLD
nQILIM2
OVP
OTP
V
CCOVP
+
I
OTP
Fault
7
Brownout
VCC(reset)
S
S
S
S
S
S
PILIM2
QRDRV
+
V
QZCD
15
Latch
Fault
Logic
Auto−recovery
QOVLD
t QOVLD
QILIM1
LEB1
OVP
R
R
V
QZCD
+
V
Fault(OVP)
Temperature
OTP
nQILIM2
Counter
TSD
QILIM2
V
QILIM1
LEB2
+
V
Fault(OTP_in)
V
QILIM2
Figure 2. NCL30030 Functional Block Diagram
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3
+
−
I QCT
6
QCT
R
QFB
QFB
8
GND
−
−
I
QCS
11
QCS
NCL30030
Table 1. PIN FUNCTION DESCRIPTION
Pin Out
1
2
3
4
5
MULT
PControl
PONOFF
Name
BO/HV
Function
Performs input brown−out detection and line voltage range detection.
Removed for creepage distance.
This is the output of the multiplication of the BO and Control signals. A capacitor should be put on this
pin for filtering. Suggested values from 1 nF − 20 nF.
Output of the PFC transconductance error amplifier. A compensation network is connected between
this pin and ground to set the loop bandwidth.
A resistor between this pin and ground sets the PFC turn off threshold. The voltage on this pin is
compared to an internal voltage signal proportional to the output power. The PFC disabled threshold
is determined by the resistor on this pin and the internal pull–up current source, I
PONOFF
.
An external capacitor sets the frequency in VCO mode for the QR flyback controller.
The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds.
A precise pull up current source allows direct interface with an NTC thermistor. Fault detection trig-
gers a latch or auto−recovery depending on device option.
Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
Input to the demagnetization detection comparator for the QR Flyback controller. Also used to set the
overpower compensation.
Supply input.
Input to the cycle−by−cycle current limit comparator for the QR Flyback section.
QR flyback controller switch driver.
PFC controller switch driver.
Input to the cycle−by−cycle current limit comparator for the PFC section. Also used to perform the
demagnetization detection for the PFC controller.
Ground reference.
PFC feedback input from external resistor divider used to sense the PFC bulk voltage. This pin volt-
age is compared to an internal reference. There are three different reference voltage combinations
depending on ac mains voltage and version of the part.
6
7
QCT
Fault
8
9
10
11
12
13
14
15
16
QFB
QZCD
VCC
QCS
QDRV
PDRV
PCS/PZCD
GND
PFB
Table 2. NCL30030 DEVICE OPTIONS
Device
NCL30030B1DR2G
NCL30030B2DR2G
NCL30030B3DR2G
NCL30030A1DR2G*
NCL30030A2DR2G*
NCL30030A3DR2G*
Flyback Overload Protection
Auto−Recovery
Auto−Recovery
Auto−Recovery
Latch
Latch
Latch
Fault OTP
Auto−Recovery
Auto−Recovery
Auto−Recovery
Latch
Latch
Latch
PFC Reference Voltage
(High Line / Low Line)
3.55 / 2 V
4/2V
4/4V
3.55 / 2 V
4/2V
4/4V
*Please contact local sales representative for availability
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NCL30030
Table 3. MAXIMUM RATINGS
(Notes 1 through
6)
Rating
High Voltage Brownout Detector Input Voltage
High Voltage Brownout Detector Input Current
PFC Low Voltage Feedback Input Voltage
PFC Low Voltage Feedback Input Current
PFC Zero Current Detection and Current Sense Input Voltage (Note 1)
PFC Zero Current Detection and Current Sense Input Current
PFC Control Input Voltage
PFC Control Input Current
Supply Input Voltage
Supply Input Current
Supply Input Voltage Slew Rate
Fault Input Voltage
Fault Input Current
PFC Multiplier pin
PFC Multiplier pin
QR Flyback Zero Current Detection Input Voltage
QR Flyback Zero Current Detection Input Current
QR Feedback Input Voltage
QR Feedback Input Current
QR Flyback Current Sense Input Voltage
QR Flyback Current Sense Input Current
QR Flyback Feedback Input Voltage
QR Flyback Feedback Input Current
PFC Driver Maximum Voltage (Note 2)
PFC Driver Maximum Current
Flyback Driver Maximum Voltage (Note 2)
Flyback Driver Maximum Current
PFC ON/OFF Threshold Adjust Input Voltage
PFC ON/OFF Threshold Adjust Input Current
Operating Junction Temperature
Storage Temperature Range
Pin
1
1
16
16
14
14
4
4
10
10
10
7
7
3
3
9
9
6
6
11
11
8
8
13
13
12
12
5
5
N/A
N/A
Symbol
V
BO/HV
I
BO/HV
V
PFB
I
PFB
V
PCS/PZCD
I
PCS/PZCD
V
PControl
I
PControl
V
CC(MAX)
I
CC(MAX)
dV
CC
/dt
V
Fault
I
Fault
V
MULT
I
MULT
V
QZCD
I
QZCD
V
QCT
I
QCT
V
QCS
I
QCS
V
QFB
I
QFB
V
PDRV
I
PDRV(SRC)
I
PDRV(SNK)
V
QDRV
I
QDRV(SRC)
I
QDRV(SNK)
V
PONOFF
I
PONOFF
T
J
T
STG
Value
−0.3 to 700
20
−0.3 to 9
0.5
−0.3 to V
PCS/PZCD(MAX)
−2/+5
−0.3 to 5
10
−0.3 to 30
30
1
−0.3 to (V
CC
+ 1.25)
10
−0.3 to 10
3
−0.9 to (V
CC
+ 1.25)
−2/+5
−0.3 to 10
10
−0.3 to 10
10
−0.3 to 10
10
−0.3 to V
PDRV(high2)
500
800
−0.3 to V
QDRV(high2)
500
800
−0.3 to 10
10
−40 to 125
–60 to 150
Unit
V
mA
V
mA
V
mA
V
mA
V
mA
V/ms
V
mA
V
mA
V
mA
V
mA
V
mA
V
mA
V
mA
V
mA
V
mA
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
1. V
PCS/PZCD(MAX)
is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks
a current equal to (V
PCS/PZCD
− 5 V)/(2 kW). A V
PSC/PZCD
of 7 V generates a sink current of approximately 1 mA.
2. Maximum driver voltage is limited by the driver clamp voltage, V
XDRV(high2)
, when V
CC
exceeds the driver clamp voltage. Otherwise,
the maximum driver voltage is V
CC
.
3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond
those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied.
Functional operation should be restricted to the Recommended Operating Conditions.
4. This device contains Latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +100/−100 mA.
5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm
2
of 2 oz copper traces and heat
spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.
6. Pin 1 is rated to the maximum voltage of the part, or 700 V.
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