S i 5 3 4 7 /4 6
D
U AL
/Q
UA D
DSPLL A
NY
- F
RE QU EN CY
, A
NY
-O
UT P UT
J
ITTER
A
TT E NU AT OR S
Features
Four or two independent DSPLLs in a
single monolithic IC
Each DSPLL generates any output
frequency from any input frequency
Input frequency range:
Differential: 8 kHz to 750 MHz
LVCMOS: 8 kHz to 250 MHz
Output frequency range:
Differential: up to 712.5 MHz
LVCMOS: up to 250 MHz
Ultra low jitter:
<100 fs typ (12 kHz–20 MHz)
Flexible crosspoints route any input to
any output clock
Programmable jitter attenuation
bandwidth per DSPLL: 0.1 Hz to 4 kHz
programming range
Highly configurable outputs compatible
with LVDS, LVPECL, LVCMOS, CML,
and HCSL with programmable signal
amplitude
Status monitoring (LOS, OOF, LOL)
Hitless input clock switching: automatic
or manual
Locks to gapped clock inputs
Automatic free-run and holdover modes
Fastlock feature for low nominal
bandwidths
Glitchless on-the-fly DSPLL frequency
changes
DCO mode: as low as 0.01 ppb steps
per DSPLL
Core voltage:
V
DD
: 1.8 V ±5%
V
DDA
: 3.3 V ±5%
Independent output clock supply pins:
3.3, 2.5, or 1.8 V
Output-output skew:
<20 ps (typ) per DSPLL
Serial interface: I
2
C or SPI
In-circuit programmable with non-volatile
OTP memory
ClockBuilder
TM
Pro software tool
simplifies device configuration
Si5347: Quad DSPLL, 4 input,
4 or 8 output, 64 QFN
Si5346: Dual DSPLL, 4 input,
4 output, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
IN0
9x9 mm
7x7 mm
Ordering Information:
See section 8
Functional Block Diagram
XTAL/
REFCLK
Si5347
XA
OSC
XB
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
IN3
÷FRAC
OUT0
OUT1
Device Selector Guide
Grade
Si5347A
Si5347C
Si5346A
Si5347B
Si5347D
Si5346B
PLLs/OUTs
4/8
4/4
2/4
4/8
4/4
2/4
Max Output Freq
712.5 MHz
712.5 MHz
712.5 MHz
350 MHz
350 MHz
350 MHz
Frequency Synthesis Modes
Integer + Fractional
Integer + Fractional
Integer + Fractional
Integer + Fractional
Integer + Fractional
Integer + Fractional
÷FRAC
DSPLL
A
DSPLL
B
DSPLL
C
DSPLL
D
Si5347C/D
OUT2
OUT3
OUT4
OUT5
IN1
÷FRAC
IN2
÷FRAC
Si5347A/B
÷INT
÷INT
OUT6
OUT7
NVM
I C/SPI
Control/
Status
2
Applications
OTN Muxponders and Transponders
10/40/100G network line cards
GbE/10 GbE/100 GbE Synchronous
Ethernet (ITU-T G.8262)
Carrier Ethernet switches
Broadcast video
XTAL/
R EFC LK
S i5 3 4 6
XA
OSC
XB
Description
IN 0
÷FR A C
÷ IN T
÷ IN T
÷ IN T
÷ IN T
OUT0
OUT1
OUT2
OUT3
The Si5347 is a high performance jitter attenuating clock multiplier which integrates four
any-frequency DSPLLs for applications that require maximum integration and independent
timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each DSPLL has
access to any of the four inputs and can provide low jitter clocks on any of the device
outputs. Based on 4
th
generation DSPLL technology, these devices provide any-frequency
conversion with typical jitter performance under 100 fs. Each DSPLL supports independent
free-run, holdover modes of operation, as well as automatic and hitless input clock
switching. The Si5347/46 is programmable via a serial interface with in-circuit
programmable non-volatile memory so that it always powers up in a known configuration.
Programming the Si5347/46 is easy with Silicon Labs’
ClockBuilder Pro
software. Factory
pre-programmed devices are also available.
IN 1
÷FR A C
DSPLL
A
DSPLL
B
IN 2
÷FR A C
IN 3
÷FR A C
NVM
I C /S P I
C o n tro l/
S ta tu s
2
Rev. 1.1 9/15
Copyright © 2015 by Silicon Laboratories
Si5347/46
Si5347/46
T
ABLE O F
C
ONTENTS
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Typical Operating Characteristics (Jitter and Phase Noise) . . . . . . . . . . . . . . . . . . . . . 22
4. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4. Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.13. How to Enable Features and/or Configuration Settings Not Available in
ClockBuilder Pro for Factory Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . 42
6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
9.1. Si5347 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
9.2. Si5346 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2
Rev. 1.1
Si5347/46
1. Typical Application Schematic
OTN Muxponder
Client #1
Data
PHY
Clock
PD
÷
LPF
M
n_A
M
d_A
DSPLL A
Client #2
Data
PHY
Clock
PD
÷
LPF
M
n_B
M
d_B
DSPLL B
Si5347
10GbE
Gapped Clock
Non-gapped
Jitter Attenuated Clock
10GbE
40G OTN
Gapped Clock
OTN
De-Mapper
Client #3
Data
Non-gapped
Jitter Attenuated Clock
PHY
Clock
PD
Gapped Clock
÷
LPF
M
n_C
M
d_C
DSPLL C
Client #4
Data
PHY
Clock
PD
÷
LPF
M
n_D
M
d_D
DSPLL D
Non-gapped
Jitter Attenuated Clock
10GbE
10GbE
Gapped Clock
Non-gapped
Jitter Attenuated Clock
Figure 1. Using the Si5347 to Clean Gapped Clocks in an OTN Application
Rev. 1.1
3
Si5347/46
2. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%,T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Junction Temperature
Core Supply Voltage
Output Driver Supply Voltage
Symbol
T
A
TJ
MAX
V
DD
V
DDA
V
DDO
Min
–40
—
1.71
3.14
3.14
2.38
1.71
Typ
25
—
1.80
3.30
3.30
2.50
1.80
3.30
1.80
Max
85
125
1.89
3.47
3.47
2.62
1.89
3.47
1.89
Unit
°C
°C
V
V
V
V
V
V
V
Status Pin Supply Voltage
V
DDS
3.14
1.71
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%, V
DDO
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
Symbol
I
DD
Test Condition
Si5347
Si5346
Notes
1, 2
Min
—
—
—
Typ
175
170
120
120
Max
240
230
130
130
Unit
mA
mA
mA
mA
I
DDA
Si5347
Si5346
Notes:
1.
Si5347 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2.
Si5346 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3.
Differential outputs terminated into an AC coupled 100
load.
4.
LVCMOS outputs measured into a 5-inch 50
PCB trace with 5 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the
Si5347/46 Family Reference Manual
for
more details on register settings.
5.
Detailed power consumption for any configuration can be estimated using
ClockBuilder Pro
when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Differential Output Test Configuration
I
DDO
OUT
OUT
50
0.1 µF
50
4.7 pF
56
LVCMOS Output Test Configuration
Trace length 5
inches
0.1 µF
50
100
499
4.7 pF
I
DDO
OUT
OUT
0.1 µF
50
Scope Input
56
50
499
0.1 µF
50
Scope Input
4
Rev. 1.1
Si5347/46
Table 2. DC Characteristics (Continued)
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%, V
DDO
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter
Output Buffer Supply Current
Symbol
I
DDO
Test Condition
LVPECL Output
3
@ 156.25 MHz
LVDS Output
3
@ 156.25 MHz
3.3V LVCMOS
4
output
@ 156.25 MHz
2.5V LVCMOS
4
output
@ 156.25 MHz
1.8V LVCMOS
4
output
@ 156.25 MHz
Min
—
—
—
—
—
—
—
Typ
21
15
21
16
12
980
840
Max
25
18
25
18
13
1160
1000
Unit
mA
mA
mA
mA
mA
mW
mW
Total Power Dissipation
P
d
Si5347
Si5346
Note
1,5
Note
2,5
Notes:
1.
Si5347 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2.
Si5346 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3.
Differential outputs terminated into an AC coupled 100
load.
4.
LVCMOS outputs measured into a 5-inch 50
PCB trace with 5 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the
Si5347/46 Family Reference Manual
for
more details on register settings.
5.
Detailed power consumption for any configuration can be estimated using
ClockBuilder Pro
when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Differential Output Test Configuration
I
DDO
OUT
OUT
50
0.1 µF
50
4.7 pF
56
LVCMOS Output Test Configuration
Trace length 5
inches
0.1 µF
50
100
499
4.7 pF
I
DDO
OUT
OUT
0.1 µF
50
Scope Input
56
50
499
0.1 µF
50
Scope Input
Rev. 1.1
5
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