PL902xxx
Revision 1.1
General Description
The PL902xxx series is a low-power, small form-factor,
high-performance OTP-based device and a member of
Micrel’s JitterBlocker, factory programmable jitter
attenuators. The JitterBlocker product family cleans any
deterministic jitter, thereby improving the peak-to-peak
jitter, accumulated jitter, and even the phase noise. The
PL902xxx is capable of reducing thousands of
picoseconds of period jitter in a clock to a level below
100ps peak-to-peak, making that clock usable for many
more applications.
The PL902xxx operates on a single 2.5V or 3.3V supply,
consumes little power, and is housed in a small SOT23
package for a broad range of applications. Programmable
I/O pins can be configured as output enable (OE),
configuration select (CSEL), power down (PDB) input, or
CLK1 (2) output. The power down feature of PL902xxx,
when activated, allows the IC to consume less than 10µA
of power, while its programming flexibility allows filtering of
any clock frequency, up to 200MHz.
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
Features
Lowest power and smallest programmable jitter
attenuator
Input/output frequency up to 200MHz
I/O pins can be configured as output enable (OE),
frequency switching (CSEL), power down (PDB) input,
or CLK1(2) output.
<10µA current consumption with PDB active
Operating temperature range from –40C to +85C
Available in 6-pin SOT23 GREEN/RoHS-compliant
packages.
Related devices:
PL903xxx: Single-ended input, differential output, and
phase noise cleaning.
PL904xxx: Differential input, two differential outputs,
and phase noise cleaning
Applications
IEEE1588 GPIO clock cleanup
FPGA-generated clock cleanup
1/10/40/100 Gigabit Ethernet (GbE)
SONET/SDH
PCI-Express
CPRI/OBSAI wireless base stations
Fibre Channel
SAS/SATA
DIMM
Block Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
August 1, 2014
Revision 1.1
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL902xxx
Ordering Information
Part Number
PL902xxxUSY TR
Marking
K2XXX
Shipping
Tape and Reel
Junction Temp. Range
–40° to +85°C
Package
SOT23-6L
Pin Configuration
SOT23-6L (3mm × 3mm × 1.35mm)
Pin Description
Pin Number
1
2
3
4
5
6
Pin Name
PDB, OE,
CLK1
GND
REF_IN
VDD
CSEL, CLK2
CLK0
Pin Type
I/O
GND
I, (SE)
PWR
I/O
O
LVCMOS
LVCMOS
LVCMOS
Pin Level
LVCMOS
Pin Function
Customizable pin: power down or output enable control
input with pull-up or clock output.
Power supply ground
Reference clock input
Power supply
Customizable pin: configuration select control input with
pull-up or clock output.
Clock output
Key Programming Parameters
CLK[0:2]
Output Frequency
CLK0 = REFIN
CLK1 = CLK0
CLK2 = CLK0, CLK0/2, or CLK0/4
Frequency translation is optional within the
specified frequency range.
Output Drive Strength
Three optional drive strengths to choose
from:
Low: 4mA
Standard: 8mA (default)
High: 16mA
Programmable
Input/Output
One output pin can be configured as:
OE – input
PDB – input
CSEL – input
CLK1, 2 – output
August 1, 2014
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Revision 1.1
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL902xxx
Functional Description
The PL902xxx series is a highly featured, very flexible, advanced programmable jitter filter design for high performance,
low-power, small form-factor applications. The PL902xxx accepts a reference clock input between 1MHz and 200MHz and
is capable of producing up to three outputs in the 5MHz to 200MHz range. The most common configuration will be
comprised of the same input and output frequency, but this flexible design also allows frequency translation from one
frequency to another frequency as long as both frequencies are within the specified ranges for input and output.
Jitter Filter Programming
Typically, the jitter filter settings will be optimized for one
particular input and output frequency, but the flexible
design also allows configurations for a certain frequency
range, up to one octave wide.
The typical bandwidth of the jitter filter is 4kHz. This means
that jitter frequency components above 4kHz will be
attenuated. In case of frequency translation, the bandwidth
may be slightly different.
Clock Output (CLK0)
CLK0 is the main clock output. The output drive level can
be programmed to low drive (4mA), standard drive (8mA)
or high drive (16mA). The maximum output frequency is
200MHz at 3.3V operation and 167MHz at 2.5V operation.
Clock Output (CLK1, CLK2)
The CLK1 and CLK2 feature allows the PL902xxx to have
two additional clock outputs programmed to one of the
following frequencies:
CLK1 = CLK0
CLK2 = CLK0, CLK0/2 or CLK0/4
Output Enable (OE)
The output enable feature allows the user to enable and
disable the clock output(s) by toggling the OE pin. The OE
pin incorporates a 60kΩ pull-up resistor, giving a default
condition of logic “1”.
Power Down Control (PDB)
The power down (PDB) feature allows the user to put the
PL902xxx into sleep mode. When activated (logic “0”),
PDB disables the synthesizer circuitry, counters, and all
other active circuitry. In power down mode, the IC
consumes <10µA of power. The PDB pin incorporates a
60kΩ pull-up resistor giving a default condition of logic “1”.
Configuration Select (CSEL)
The configuration select (CSEL) feature allows the
PL902xxx to switch between two pre-programmed
configurations allowing the device on-the-fly frequency
switching. The CSEL pin incorporates a 60kΩ pull-up
resistor giving a default condition of logic “1”.
Examples for this feature are:
Select between two frequencies or two frequency
ranges.
Select between two frequency translations, like 1:1
and 1:2.
CLK1 and CLK2 allow the same output drive level
programming as CLK0. Because of the extra /2 and /4
settings, CLK2 is capable of going down to 1.25MHz. In
case only an output clock of <5MHz is needed, CLK0 and
CLK1 can be disabled.
August 1, 2014
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Revision 1.1
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or (408) 955-1690
Micrel, Inc.
PL902xxx
Absolute Maximum Ratings
(1)
Supply Voltage (V
DD
) ................................................... +4.6V
Input Voltage (V
IN
) ................................
0.5V
to V
DD
+ 0.5V
Lead Temperature (soldering, 20s) ............................ 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (Ts)......................... –65°C to +150°C
Operating Ratings
(2)
Supply Voltage (V
DD
) ................................ +2.25V to +3.63V
Ambient Temperature (T
A
) .......................... –40°C to +85°C
Junction Thermal Resistance
SOT23 (
JA
), Still-Air ........................................ 195°C/W
DC Electrical Characteristics
V
DD
= 3.3V
±
10% or 2.5V
±
10%; C
L
= 15pF; T
A
= 25°C,
bold
values indicate –40°C≤ T
A
≤ +85°C, unless noted.
Symbol
I
DD
I
DD
V
DD
t
PU
I
OLD
I
OSD
I
OHD
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to function outside its operating ratings.
Parameter
Supply current, dynamic
Supply current, dynamic
Operating voltage
Power supply ramp
Output current, low drive
Output current, standard drive
Output current, high drive
Condition
V
DD
= 3.3V, 30MHz, load = 15pF
When PDB = 0
Min.
Typ.
12
Max.
18
<10
Units
mA
µA
V
ms
mA
mA
mA
2.25
Time for V
DD
to reach 90% V
DD
. Power
ramp must be monotonic.
V
OL
= 0.4V, V
OH
= V
DD
– 0.9V, V
DD
= 3.3V
V
OL
= 0.4V, V
OH
= V
DD
– 0.9V, V
DD
= 3.3V
V
OL
= 0.4V, V
OH
= V
DD
– 0.9V, V
DD
= 3.3V
0.001
4
8
16
3.63
100
August 1, 2014
4
Revision 1.1
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL902xxx
AC Electrical Characteristics
V
DD
= 3.3V ±10% or 2.5V ±10%; C
L
= 15pF; T
A
= 25°C,
bold
values indicate –40°C≤ T
A
≤ +85°C, unless noted.
Parameter
Input (REFIN) frequency
Input signal amplitude
Input signal amplitude
Condition
3.3V operation
2.5V operation
Internally AC-coupled (high frequency)
Internally AC-coupled (low frequency)
3.3V ≤ 50MHz, 2.5V ≤ 40MHz
CLK0 and CLK1, 3.3V operation
Output frequency
CLK0 and CLK1, 2.5V operation
CLK2, 3.3V operation
CLK2, 2.5V operation
Settling time
Output enable time
Output rise time
Output fall time
Duty Cycle
Period jitter, peak-to-peak
(10,000 samples measured)
Jitter attenuation bandwidth
Notes:
3. Jitter performance can be considered the noise floor of the device. Jitter cannot be attenuated below this value.
(3)
Min.
1
1
0.8
0.1
5
5
1.25
1.25
Typ.
Max.
200
167
V
DD
V
DD
200
167
200
167
1
10
1
Units
MHz
MHz
V
PP
V
PP
MHz
MHz
MHz
MHz
ms
ns
ms
ns
ns
%
ps
kHz
At power up (after V
DD
increases over 2.25V)
OE function: T
A
= 25ºC, 15pF load. Add one clock
period to this measurement for a usable clock output.
PDB function: T
A
= 25ºC, 15pF load.
15pF load, 10/90% V
DD
, high drive, 3.3V
15pF load, 10/90% V
DD
, high drive, 3.3V
@ 2.5V and 3.3V over entire frequency range.
Threshold = V
DD
/2
With capacitive decoupling between VDD and GND
CLK0 = REFIN
45
1.2
1.2
50
75
4
1.7
1.7
55
August 1, 2014
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or (408) 955-1690
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