74HC194
4-bit bidirectional universal shift register
Rev. 3 — 29 November 2016
Product data sheet
1. General description
The 74HC194 is a 4-bit bidirectional universal shift register. The synchronous operation of
the device is determined by the mode select inputs (S0, S1). In parallel load mode (S0
and S1 HIGH) data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is
transferred to the Q0 to Q3 outputs. When S0 is HIGH and S1 is LOW data is entered
serially via DSL and shifted from left to right; when S0 is LOW and S1 is HIGH data is
entered serially via DSR and shifted from right to left. DSR and DSL allow multistage shift
right or shift left data transfers without interfering with parallel load operation. If both S0
and S1 are LOW, existing data is retained in a hold mode. Mode select and data inputs
are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP).
Therefore, the only timing restriction is that the mode control and selected data inputs
must be stable one set-up time prior to the positive transition of the clock pulse. When
LOW, the asynchronous master reset (MR) overrides all other input conditions and forces
the Q outputs LOW. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC194: CMOS level
Shift-left and shift right capability
Synchronous parallel and serial data transfer
Easily expanded for both serial and parallel operation
Asynchronous master reset
Hold (‘do nothing’) mode
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
Nexperia
74HC194
4-bit bidirectional universal shift register
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC194D
74HC194DB
40 C
to +125
C
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
SOT338-1
Type number
SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC194
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 29 November 2016
2 of 17
Nexperia
74HC194
4-bit bidirectional universal shift register
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO16
Fig 6.
Pin configuration SSOP16
74HC194
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 29 November 2016
3 of 17
Nexperia
74HC194
4-bit bidirectional universal shift register
5.2 Pin description
Table 2.
Symbol
MR
DSR
D0, D1, D2, D3
DSL
GND
S0, S1
CP
Q0, Q1, Q2, Q3
V
CC
Pin description
Pin
1
2
3, 4, 5, 6
7
8
9, 10
11
15, 14, 13, 12
16
Description
asynchronous master reset (active LOW)
serial data input (shift right)
parallel data inputs
serial data input (shift left)
ground (0 V)
mode control inputs
clock input (LOW-to-HIGH, edge triggered)
parallel outputs
positive supply voltage
6. Functional description
Table 3.
Function table
[1]
Inputs
CP
Reset (clear)
Hold (do nothing)
Shift left
Shift right
Parallel load
[1]
Operating mode
Outputs
MR
L
H
H
H
H
H
H
S1
X
l
h
h
l
l
h
S0
X
l
l
l
h
h
h
DSR
X
X
X
X
l
h
X
DSL
X
X
l
h
X
X
X
Dn
X
X
X
X
X
X
dn
Q0
L
q0
q1
q1
L
H
d0
Q1
L
q1
Q2
L
q2
q3
q3
q1
q1
d2
Q3
L
q3
L
H
q2
q2
d3
X
X
q2
q2
q0
q0
d1
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q, d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW-to-HIGH CP transition;
X = don’t care;
= LOW-to-HIGH clock transition.
74HC194
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 29 November 2016
4 of 17
Nexperia
74HC194
4-bit bidirectional universal shift register
Typical timing sequence:
Typical clear-load; shift-right; shift-left; inhibit and clear timing sequences.
Fig 7.
Typical timing sequence
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO16 package
SSOP16 package
[1]
For SO16 packages: above 70
C
the value of P
tot
derates linearly at 8 mW/K.
For SSOP16 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
[1]
[1]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
-
-
Max
+7.0
20
20
25
+50
-
+150
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
74HC194
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 29 November 2016
5 of 17
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