a
FEATURES
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
APPLICATIONS
Multiple Path Timing Deskew for ATE
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
INPUT
3
Octal Sample-and-Hold
with Multiplexed Input
SMP08*
FUNCTIONAL BLOCK DIAGRAM
(LSB)
A
11
B
10
(MSB)
C
9
INH
6
8 DGND
1 OF 8 DECODER
16 V
DD
SW
13 CH
0
OUT
SW
14 CH
1
OUT
SW
15 CH
2
OUT
SW
12 CH
3
OUT
SW
1
CH
4
OUT
SW
5
CH
5
OUT
SW
2
CH
6
OUT
GENERAL DESCRIPTION
The SMP08 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP08 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±
1/2 LSB in less than 7 microseconds. The SMP08’s output
swing includes the negative supply in both single and dual sup-
ply operation.
The SMP08 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP08 ideal for
calibration requirements that have previously required an
ASIC, or high cost multiple D/A converters.
*Protected
by U.S. Patent No. 4,739,281.
SW
HOLD CAPS
(INTERNAL)
4 CH
7
OUT
7 V
SS
SMP08
The SMP08 is also ideally suited for a wide variety of sample-
and-hold applications including amplifier offset or VCA gain
adjustments. One or more SMP08s can be used with single or
multiple DACs to provide multiple set points within a system.
The SMP08 offers significant cost and size reduction over dis-
crete designs. It is available in a 16-pin plastic DIP, or surface-
mount SOIC package.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
SMP08–SPECIFICATIONS
(@ V
ELECTRICAL CHARACTERISTICS
Parameter
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
2
Acquisition Time
3
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
Capacitive Load Stability
Analog Crosstalk
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Symbol
V
OS
V
HS
∆V
CH
/∆t
I
SOURCE
I
SINK
= +5 V, V
SS
= –5 V, DGND = 0 V, R
L
= No Load, T
A
= –40 C to +85 C for SMP08F,
unless otherwise noted)
DD
Conditions
–3 V
≤
V
IN
≤
+3 V
T
A
= +25°C, V
IN
= 0 V
–40°C
≤
T
A
≤
+85°C, V
IN
= 0 V
V
IN
= 0 V, T
A
= +25°C to +85°C
V
IN
= 0 V, T
A
= –40°C
T
A
= +25°C, V
IN
= 0 V
V
IN
= 0 V
1
V
IN
= 0 V
1
R
L
= 20 kΩ
Min
Typ
0.01
2.5
3.5
2.5
2
Max
10
20
4
5
20
+3.0
1.2
0.5
–3.0
2.4
Units
%
mV
mV
mV
mV
mV/s
mA
mA
V
V
V
µA
µs
µs
ns
ns
ns
V/µs
pF
dB
dB
mA
mA
V
INH
V
INL
I
IN
t
AQ
t
H
t
CH
t
DCS
t
IR
SR
V
IN
= 2.4 V
T
A
= +25°C, –3 V to +3 V to 0.1%
To
±
1 mV of Final Value
0.5
3.6
1
90
45
90
3
500
–72
60
75
4
5
0.8
1
7
<30% Overshoot
–3 V to +3 V Step
PSRR
I
DD
V
S
=
±
5 V to
±
6 V
T
A
= +25°C
–40°C
≤
T
A
≤
+85°C
7.5
9.5
ELECTRICAL CHARACTERISTICS
Parameter
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
2
Acquisition Time
3
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
Capacitive Load Stability
Analog Crosstalk
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Symbol
V
OS
V
HS
∆V
CH
/∆t
I
SOURCE
I
SINK
(@ V
DD
= +12 V, V
SS
= 0 V, DGND = 0 V, R
L
= No Load, T
A
= –40 C to +85 C for SMP08F,
unless otherwise noted)
Conditions
60 mV
≤
V
IN
≤
10 V
T
A
= +25°C, V
IN
= 6 V
–40°C
≤
T
A
≤
+85°C, V
IN
= 6 V
V
IN
= 6 V, T
A
= +25°C to +85°C
V
IN
= 6 V, T
A
= –40°C
T
A
= +25°C, V
IN
= 6 V
V
IN
= 6 V
1
V
IN
= 6 V
1
R
L
= 20 kΩ
R
L
= 10 kΩ
Min
Typ
0.01
2.5
3.5
2.5
2
1.2
0.5
0.06
0.06
2.4
V
IN
= 2.4 V
T
A
= +25°C, 0 V to 10 V to 0.1%
–40°C
≤
T
A
≤
+85°C
To
±
1 mV of Final Value
0.5
3.5
3.75
1
90
45
90
4
500
–72
75
6.0
8.0
0.8
1
4.25
6.00
Max
10
20
4
5
20
10.0
9.5
Units
%
mV
mV
mV
mV
mV/s
mA
mA
V
V
V
V
µA
µs
µs
µs
ns
ns
ns
V/µs
pF
dB
dB
mA
mA
V
INH
V
INL
I
IN
t
AQ
t
H
t
CH
t
DCS
t
IR
SR
R
L
= 20 kΩ
4
<30% Overshoot
0 V to 10 V Step
10.8 V
≤
V
DD
≤
13.2 V
T
A
= +25°C
–40°C
≤
T
A
≤
+85°C
3
PSRR
I
DD
60
8.0
10.0
NOTES
1
Outputs are capable of sinking and sourcing over 20 mA but offset is guaranteed at specified load levels.
2
All input control signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3
This parameter is guaranteed without test.
4
Slew rate is measured in the sample mode with 0 V to 10 V step from 20% to 80%.
Specifications subject to change without notice.
–2–
REV. D
SMP08
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
LOGIC
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
V
IN
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
V
OUT
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
(Not Short-Circuit Protected)
Operating Temperature Range
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Package Type
16-Pin Plastic DIP (P)
16-Pin SOIC (S)
JA
*
JC
Model
SMP08FP
SMP08FS
Temperature
Range
–40°C to +85°C
–40°C to +85°C
Package
Description
Plastic DIP
SO-16
Package
Option
N-16
R-16A
PIN CONNECTIONS
CH
4
OUT 1
CH
6
OUT 2
INPUT 3
CH
7
OUT 4
16 V
DD
15 CH
2
OUT
14 CH
1
OUT
Units
°C/W
°C/W
76
92
33
27
13 CH
0
OUT
TOP VIEW
CH
5
OUT 5 (Not to Scale) 12 CH
3
OUT
INH 6
V
SS
7
DGND 8
11 A CONTROL
10 B CONTROL
9 C CONTROL
SMP08
*θ
JA
is specified for worst case mounting conditions, i.e.,
θ
JA
is specified for device
in socket for plastic DIP package;
θ
JA
is specified for device soldered to printed
circuit board for SO package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP08 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
SMP08–Typical Performance Characteristics
1000
V
DD
= +12V
V
SS
= 0V
V
I N
= +5V
R
L
= 10kΩ
3
1800
1600
V
DD
= +12V
V
SS
= 0V
T
A
= +125
°
C
NO LOAD
1400
2
100
DROOP RATE – mV/s
DROOP RATE – mV/s
1
DROOP RATE – mV/s
10
0
1200
–1
V
DD
= +12V
V
SS
= 0V
–2
T
A
= +25
°
C
NO LOAD
–3
2 3
4
5
6 7
8
0 1
INPUT VOLTAGE – Volts
1000
1
800
0.1
–55 –35 –15
600
9
10
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
5
25 45 65 85 105 125
TEMPERATURE –
°
C
Figure 1. Droop Rate vs. Temperature
Figure 2. Droop Rate vs. Input Voltage
Figure 3. Droop Rate vs. Input Voltage
2
1
HOLD STEP – mV
V
DD
= +12V
V
SS
= 0V
T
A
= +25
°
C
NO LOAD
0
2
V
DD
= +12V
V
SS
= 0V
V
I N
= +5V
NO LOAD
7
1
V
SS
= 0V
T
A
= +25
°
C
NO LOAD
6
HOLD STEP – mV
0
SLEW RATE – V/µs
–SR
5
+SR
4
–1
–1
–2
–2
–3
–3
3
10
–4
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
–4
–55
–35
–15
5
25
45
TEMPERATURE –
°
C
65
85
11
12
13
14
15
V
DD
– Volts
16
17
18
Figure 4. Hold Step vs. Input Voltage
Figure 5. Hold Step vs. Temperature
Figure 6. Slew Rate vs. V
DD
4
2
OFFSET VOLTAGE – mV
0
–2
–4
–6
–8
–10
0
1
2
R
L
= 20kΩ
R
L
= 10kΩ
R
L
=
V
DD
= +12V
V
SS
= 0V
OFFSET VOLTAGE – mV
20
15
10
5
0
–5
–10
–15
–20
V
DD
= +12V
V
SS
= 0V
NO LOAD
OFFSET VOLTAGE – mV
T
A
= +85
°
C
4
2
0
–2
–4
–6
–8
–10
R
L
= 10kΩ
R
L
=
V
DD
= +12V
V
SS
= 0V
∞
T
A
= +25
°
C
NO LOAD
∞
T
A
= –40
°
C
NO LOAD
R
L
= 20kΩ
R
L
=
∞
R
L
= 10kΩ
R
L
= 20kΩ
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
Figure 7. Offset Voltage vs. Input
Voltage
Figure 8. Offset Voltage vs. Input
Voltage
Figure 9. Offset Voltage vs. Input
Voltage
–4–
REV. D
Typical Performance Characteristics–SMP08
0
–1
V
DD
= +12V
V
SS
= 0V
14
12
SUPPLY CURRENT – mA
V
SS
= 0V
NO LOAD
REJECTION RATIO – dB
90
80
70
60
50
40
30
20
10
–PSRR
+PSRR
V
DD
= +12V
V
SS
= 0V
V
IN
= +6V
T
A
= +25
°
C
NO LOAD
OFFSET VOLTAGE – mV
–2
–3
–4
–5
–6
–7
–8
–55 –35 –15
V
I N
= +5V
R
L
= 10kΩ
10
+85
°
C
8
+25
°
C
6
–40
°
C
4
5
25
45
65
85 105 125
2
4
6
8
12
V
DD
– Volts
10
14
16
18
0
10
100
TEMPERATURE –
°
C
1k
10k
100k
FREQUENCY – Hz
1M
Figure 10. Offset Voltage vs.
Temperature
Figure 11. Supply Current vs. V
DD
Figure 12. Sample Mode Power
Supply Rejection
2
1
0
GAIN – dB
–1
V
DD
= +12V
V
SS
= 0V
T
A
= +25
°
C
NO LOAD
90
45
PHASE SHIFT – Degrees
0
–45
35
30
OUTPUT IMPEDANCE –
Ω
V
DD
= +12V
V
SS
= 0V
T
A
= +25
°
C
NO LOAD
25
20
15
10
5
0
10
PHASE
–2
–3
GAIN
–4
–5
100
–180
–225
10M
–90
–135
1k
10k
100k
FREQUENCY – Hz
1M
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 13. Gain, Phase Shift vs.
Frequency
Figure 14. Output Impedance vs.
Frequency
15
PEAK-TO-PEAK OUTPUT – Volts
V
DD
= +6V
V
SS
= –6V
T
A
= +25
°
C
NO LOAD
REJECTION RATIO – dB
60
50
+PSRR
40
V
DD
= +12V
30 V
SS
= 0V
T
A
= +25
°
C
20 NO LOAD
10 HOLD CAPACITORS
REFERENCED TO V
SS
0
–PSRR
12
9
6
3
0
10k
1M
100k
FREQUENCY – Hz
10M
–10
10
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 15. Maximum Output Voltage
vs. Frequency
Figure 16. Hold Mode Power Supply
Rejection
REV. D
–5–
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