MC74AC74, MC74ACT74
Dual D-Type Positive
Edge-Triggered Flip-Flop
The MC74AC74/74ACT74 is a dual D−type flip−flop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q HIGH
Features
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
1
14
xxx74G
AWLYWW
14
•
Outputs Source/Sink 24 mA
•
′ACT74
Has TTL Compatible Inputs
•
These are Pb−Free Devices
V
CC
14
C
D2
13
D
2
12
CP
2
11
S
D2
10
Q
2
9
Q
2
8
1
14
TSSOP−14
DT SUFFIX
CASE 948G
1
xxx
= AC or ACT
A
= Assembly Location
WL or L = Wafer Lot
Y
= Year
WW or W = Work Week
G or
G
= Pb−Free Package
xxx
74
ALYWG
G
C
D1
D
1
Q
1
CP
1
S
D1
Q
1
S
D2
CP
2
Q
2
D
2
C
D2
Q
2
(Note: Microdot may be in either location)
1
C
D1
2
D
1
3
CP
1
4
S
D1
5
Q
1
6
Q
1
7
GND
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
,
Q
2
FUNCTION
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
January, 2015 − Rev. 8
Publication Order Number:
MC74AC74/D
MC74AC74, MC74ACT74
TRUTH TABLE
(Each Half)
Inputs
S
D
L
H
L
H
H
H
NOTE:
C
D
H
L
L
H
H
H
CP
X
X
X
D
X
X
X
H
L
X
Q
H
L
H
H
L
Q
0
Outputs
Q
L
H
H
L
H
Q
0
Q
1
S
D1
D
1
Q
1
C
D1
CP
1
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial;
= LOW-to-HIGH Clock Transition
Q
0
(Q
0
) = Previous Q(Q) before LOW-to-HIGH
Transition of Clock
Q
2
S
D2
D
2
CP
2
Q
2
CD
2
Figure 2. Logic Symbol
S
D
D
Q
CP
Q
C
D
NOTE:
This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
Figure 3. Logic Diagram
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2
MC74AC74, MC74ACT74
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink/Source Current
DC Supply Current per Output Pin
DC Ground Current per Output Pin
Storage Temperature Range
Lead temperature, 1 mm from Case for 10 Seconds
Junction temperature under Bias
Thermal Resistance (Note 2)
Power Dissipation in Still Air at 85°C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
Above V
CC
and Below GND at 85°C (Note 6)
SOIC
TSSOP
SOIC
TSSOP
(Note 1)
Parameter
Value
*0.5
to
)7.0
*0.5 v
V
I
v
V
CC
)0.5
*0.5 v
V
O
v
V
CC
)0.5
$20
$50
$50
$50
$50
*65
to
)150
260
)150
125
170
125
170
Level 1
UL 94 V−0 @ 0.125 in
> 2000
> 200
> 1000
$100
V
Unit
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
mW
I
Latch−Up
Latch−Up Performance
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
O
absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
@ 3.0 V
t
r
, t
f
Input Rise and Fall Time (Note )
′AC
Devices except Schmitt Inputs
Input Rise and Fall Time (Note )
′ACT
Devices except Schmitt Inputs
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
Output Current − Low
V
CC
@ 4.5 V
V
CC
@ 5.5 V
t
r
, t
f
T
J
T
A
I
OH
I
OL
V
CC
@ 4.5 V
V
CC
@ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
−
−
−
−
−
−
−40
−
−
Typ
5.0
5.0
−
150
40
25
10
8.0
−
25
−
−
Max
6.0
5.5
V
CC
−
−
−
−
ns/V
−
140
85
−24
24
°C
°C
mA
mA
ns/V
V
V
Unit
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. V
in
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
in
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
MC74AC74, MC74ACT74
DC CHARACTERISTICS
74AC
Symbol
Parameter
V
CC
(V)
T
A
= +25°C
Typ
V
IH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
−
−
−
0.002
0.001
0.001
−
−
−
−
−
−
−
74AC
T
A
=
−40°C to
+85°C
Unit
Conditions
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
−
−
4.0
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
−75
40
V
V
OUT
= 0.1 V
or V
CC
− 0.1 V
V
OUT
= 0.1 V
or V
CC
− 0.1 V
I
OUT
= −50
mA
V
*V
IN
= V
IL
or V
IH
−12 mA
I
OH
−24 mA
−24 mA
I
OUT
= 50
mA
V
*V
IN
= V
IL
or V
IH
12 mA
I
OL
24 mA
24 mA
V
I
= V
CC
, GND
V
OLD
= 1.65 V Max
V
OHD
= 3.85 V Min
V
IN
= V
CC
or GND
V
IL
V
V
OH
V
V
mA
mA
mA
mA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
.
AC CHARACTERISTICS
74AC
Symbol
Parameter
V
CC
*
(V)
Min
f
max
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock
Frequency
Propagation Delay
C
Dn
or S
Dn
to Q
n
or Q
n
Propagation Delay
C
Dn
or S
Dn
to Q
n
or Q
n
Propagation Delay
C
Pn
to Q
n
or Q
n
Propagation Delay
C
Pn
to Q
n
or Q
n
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
100
140
5.0
3.5
4.0
3.0
4.5
3.5
3.5
2.5
T
A
= +25°C
C
L
= 50 pF
Typ
125
160
8.0
6.0
10.5
8.0
8.0
6.0
8.0
6.0
Max
−
−
12.5
9.0
12.0
9.5
13.5
10.0
14.0
10.0
74AC
T
A
= −40°C
to +85°C
C
L
= 50 pF
Min
95
125
4.0
3.0
3.5
2.5
4.0
3.0
3.5
2.5
Max
−
−
13.0
10.0
13.5
10.5
16.0
10.5
14.5
10.5
MHz
ns
ns
ns
ns
3−3
3−6
3−6
3−6
3−6
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
Voltage Range 5.0 V is 5.0 V
±0.5
V.
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MC74AC74, MC74ACT74
AC OPERATING REQUIREMENTS
74AC
Symbol
Parameter
V
CC
*
(V)
Typ
t
s
t
h
t
w
t
rec
Set-up Time, HIGH or LOW
D
n
to CP
n
Hold Time, HIGH or LOW
D
n
to CP
n
C
Pn
or C
Dn
or S
Dn
Pulse Width
Recovery TIme
C
Dn
or S
Dn
to CP
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
1.5
1.0
−2.0
−1.5
3.0
2.5
−2.5
−2.0
T
A
= +25°C
C
L
= 50 pF
74AC
T
A
= −40°C
to +85°C
C
L
= 50 pF
Unit
Fig.
No.
Guaranteed Minimum
4.0
3.0
0.5
0.5
5.5
4.5
0
0
4.5
3.0
0.5
0.5
7.0
5.0
0
0
ns
ns
ns
ns
3−9
3−9
3−6
3−9
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
Voltage Range 5.0 V is 5.0 V
±0.5
V.
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