74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs
April 2007
74ACQ573, 74ACTQ573
Quiet Series™ Octal Latch with 3-STATE Outputs
Features
■
I
CC
and I
OZ
reduced by 50%
■
Guaranteed simultaneous switching noise level and
■
■
■
■
tm
General Description
The ACQ/ACTQ573 is a high-speed octal latch with buff-
ered common Latch Enable (LE) and buffered common
Output Enable (OE) inputs. The ACQ/ACTQ573 is func-
tionally identical to the ACQ/ACTQ373 but with inputs
and outputs on opposite sides of the package. The ACQ/
ACTQ utilizes Fairchild's Quiet Series™ technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTO™ output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
Outputs source/sink 24mA
Ordering Information
Order Number
74ACQ573SC
74ACQ573SJ
74ACQ573MTC
74ACTQ573SC
74ACTQ573SJ
74ACTQ573QSC
74ACTQ573MTC
Package
Number
M20B
M20D
MTC20
M20B
M20D
MQA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs
Logic Symbol
Functional Description
The ACQ/ACTQ573 contains eight D-type latches with
3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D-type input
changes. When LE is LOW the latches store the informa-
tion that was present on the D-type inputs at setup time
preceding the HIGH-to-LOW transition of LE. The
3-STATE buffers are controlled by the Output Enable
(OE) input. When OE is LOW, the buffers are enabled.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data
into the latches.
IEEE/IEC
Truth Table
Inputs
OE
L
L
L
H
H
=
HIGH Voltage
L
=
LOW Voltage
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of
Latch Enable
Outputs
D
H
L
X
X
LE
H
H
L
X
O
n
H
L
O
0
Z
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
2
74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
±300mA
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
DC Latch-Up Source or Sink Current
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
ACQ
ACTQ
V
I
V
O
T
A
∆
V /
∆
t
∆
V /
∆
t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
125mV/ns
Minimum Input Edge Rate, ACQ Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate, ACTQ Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
3
74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs
DC Electrical Characteristics for ACQ
T
A
=
+25°C
Symbol
V
IH
T
A
=
–40°C to +85°C
Units
V
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
± 1.0
75
–75
µA
mA
mA
µA
µA
V
V
V
Parameter
Minimum HIGH Level
Input Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Conditions
V
OUT
=
0.1V or
V
CC
– 0.1V
V
OUT
=
0.1V or
V
CC
– 0.1V
I
OUT
=
–50µA
Typ.
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
Guaranteed Limits
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IL
or V
IH
:
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
V
IN
=
V
IL
or V
IH
:
3.0
4.5
5.5
I
IN(3)
I
OLD
I
OHD
I
CC(3)
I
OZ
Maximum Input
Leakage Current
Minimum Dynamic
Output Current
(2)
Maximum Quiescent
Supply Current
Maximum 3-STATE
Leakage Current
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
I
OL
=
12mA
I
OL
=
24mA
I
OL
=
24mA
(1)
V
I
=
V
CC
, GND
V
OLD
=
1.65 V
Max
V
OHD
=
3.85 V
Min
V
IN
=
V
CC
or GND
V
I
(OE)
=
V
IL
, V
IH
;
V
I
=
V
CC
, GND;
V
O
=
V
CC
, GND
Figures 1 & 2
(4)
Figures 1 & 2
(4)
(5)
I
OH
=
–12mA
I
OH
=
–24mA
I
OH
=
–24mA
(1)
0.002
I
OUT
=
50µA
0.001
0.001
0.1
0.1
0.1
0.36
0.36
0.36
± 0.1
4.0
±0.25
40.0
±2.5
V
OLP
V
OLV
V
IHD
V
ILD
5.0
5.0
5.0
5.0
1.1
–0.6
3.1
1.9
1.5
–1.2
3.5
1.5
V
V
V
V
(5)
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
4. Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
5. Max number of Data Inputs (n) switching. (n – 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching:
5V to threshold (V
ILD
), 0V to threshold (V
IHD
), f
=
1MHz.
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
4
74ACQ573, 74ACTQ573 Quiet Series™ Octal Latch with 3-STATE Outputs
DC Electrical Characteristics for ACTQ
T
A
=
+25°C
Symbol
V
IH
V
IL
V
OH
T
A
=
–40°C to +85°C
Units
V
V
V
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
±2.5
1.5
75
–75
µA
µA
mA
mA
mA
µA
V
V
V
V
V
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Conditions
V
OUT
=
0.1V or
V
CC
– 0.1V
V
OUT
=
0.1V or
V
CC
– 0.1V
I
OUT
=
–50µA
V
IN
=
V
IL
or V
IH
:
Typ.
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
Guaranteed Limits
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
I
OH
=
–24mA
I
OH
=
–24mA
(6)
I
OUT
=
50µA
V
IN
=
V
IL
or V
IH
:
0.001
0.001
I
OL
=
24mA
I
OL
=
24mA
(6)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
;
V
O
=
V
CC
, GND
V
I
=
V
CC
– 2.1V
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
Figures 1 & 2
(8)
Figures 1 & 2
(8)
(9)
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
±0.25
0.6
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input Leakage
Current
Maximum 3-STATE
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current
(7)
Maximum Quiescent
Supply Current
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
4.0
1.1
–0.6
1.9
1.2
1.5
–1.2
2.2
0.8
40.0
(9)
Notes:
6. All outputs loaded; thresholds on input associated with output under test.
7. Maximum test duration 2.0ms, one output loaded at a time.
8. Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @ GND.
9. Max number of data inputs (n) switching. (n – 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching:
3V to threshold (V
ILD
), 0V to threshold (V
IHD
), f
=
1MHz.
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
5
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