74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs
November 1988
Revised March 2005
74AC373 • 74ACT373
Octal Transparent Latch with 3-STATE Outputs
General Description
The AC/ACT373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The flip-
flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Eight latches in a single package
s
3-STATE outputs for bus interfacing
s
Outputs source/sink 24 mA
s
ACT373 has TTL-compatible inputs
Ordering Code:
Order Number
74AC373SC
74AC373SJ
74AC373MTC
74AC373PC
74ACT373SC
74ACT373SCX_NL
(Note 1)
74ACT373SJ
74ACT373MSA
74ACT373MTC
74ACT373MTCX_NL
(Note 1)
74ACT373PC
Package
Number
M20B
M20D
MTC20
N20A
M20B
M20B
M20D
MSA20
MTC20
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering information.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicated Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009958
www.fairchildsemi.com
74AC373 • 74ACT373
Logic Symbols
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
IEEE/IEC
Truth Table
Inputs
LE
X
H
H
L
H
L
Z
X
O
0
Outputs
D
n
X
L
H
X
O
n
Z
L
H
O
0
OE
H
L
L
L
Connection Diagram
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Functional Description
The AC/ACT373 contains eight D-type latches with 3-
STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are transparent, i.e., a latch out-
put will change state each time its D-type input changes.
When LE is LOW, the latches store the information that
was present on the D-type inputs a setup time preceding
the HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2-state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74AC373 • 74ACT373
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
0.5V to
7.0V
20 mA
20 mA
0.5V to V
CC
0.5V
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
140
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
AC
ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (
'
V/
'
t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
0.5V
V
CC
0.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
0.5V
V
CC
0.5V
40
q
C to
85
q
C
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
125 mV/ns
DC Electrical Characteristics for AC
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 5)
I
OZ
Maximum Input Leakage Current
Maximum 3-STATE Current
5.5
I
OLD
I
OHD
I
CC
(Note 5)
Maximum Quiescent Supply Current
Minimum Dynamic Output Current
(Note 4)
5.5
5.5
5.5
4.0
5.5
0.002
0.001
0.001
T
A
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
Guaranteed Limits
Units
V
OUT
V
Conditions
0.1V
or V
CC
0.1V
V
OUT
0.1V
V
or V
CC
0.1V
V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
V
V
I
OH
I
OH
I
OL
I
OUT
V
IN
12 mA
24 mA
24 mA (Note 3)
50
P
A
V
IL
or V
IH
12 mA
24 mA
24 mA (Note 3)
V
CC
, GND
V
IL
, V
IH
V
CC
, GND
V
CC
, GND
1.65V Max
3.85V Min
V
CC
or GND
0.44
0.44
0.44
V
I
OL
I
OL
I
OL
V
I
V
I
V
O
r
0.1
r
0.25
r
1.0
r
2.5
75
P
A
P
A
mA
mA
V
I
(OE)
V
OLD
V
OHD
V
IN
75
40.0
P
A
Note 3:
All outputs loaded, thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
3
www.fairchildsemi.com
74AC373 • 74ACT373
DC Electrical Characteristics for ACT
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum 3-STATE
Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 7)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
4.0
0.6
5.5
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Guaranteed Limits
Units
V
V
V
V
OUT
V
OUT
I
OUT
V
IN
V
I
OH
I
OUT
V
IN
V
I
OL
I
OL
V
I
V
I
V
O
V
I
V
OLD
V
OHD
V
IN
Conditions
0.1V
0.1V
or V
CC
0.1V
or V
CC
0.1V
50
P
A
V
IL
or V
IH
24 mA
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 6)
V
CC
, GND
V
IL
, V
IH
V
CC
, GND
V
CC
2.1V
1.65V Max
3.85V Min
V
CC
I
OH
24 mA (Note 6)
V
r
0.1
r
1.0
P
A
r
0.25
r
2.5
1.5
75
P
A
mA
mA
mA
75
40.0
P
A
or GND
Note 6:
All outputs loaded; thresholds on input associated with output under test.
Note 7:
Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
V
CC
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
D
n
to O
n
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Note 8:
Voltage Range 3.3 is 3.3V
r
0.3V
Voltage Range 5.0 is 5.0V
r
0.5V
T
A
C
L
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
25
q
C
50 pF
Typ
10.0
7.0
9.5
7.0
10.0
7.5
9.5
7.0
9.0
7.0
8.5
6.5
10.0
8.0
8.0
6.5
Max
13.5
9.5
13.0
9.5
13.5
9.5
12.5
9.5
11.5
8.5
11.5
8.5
12.5
11.0
11.5
8.5
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
15.0
10.5
14.5
10.5
15.0
10.5
14.0
10.5
13.0
9.5
13.0
9.5
14.5
12.5
12.5
10.0
ns
ns
ns
ns
ns
ns
ns
ns
Units
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
www.fairchildsemi.com
4
74AC373 • 74ACT373
AC Operating Requirements for AC
V
CC
Symbol
t
S
t
H
t
W
Parameter
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width,
HIGH
Note 9:
Voltage Range 3.3 is 3.3V
r
0.3V
Voltage Range 5.0 is 5.0V
r
0.5V
T
A
C
L
Typ
3.5
2.0
25
q
C
50 pF
T
A
40
q
C to
85
q
C
C
L
50 pF
Units
(V)
(Note 9)
3.3
5.0
3.3
5.0
3.3
5.0
Guaranteed Minimum
5.5
4.0
1.0
1.0
5.5
4.0
6.0
4.5
1.0
1.0
6.0
4.5
ns
ns
ns
3.0
1.5
4.0
2.0
AC Electrical Characteristics for ACT
V
CC
Symbol
Parameter
(V)
(Note 10)
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
D
n
to O
n
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
2.0
2.5
1.5
8.0
7.5
9.0
7.5
9.5
9.0
11.0
8.5
1.5
1.5
2.5
1.0
10.5
10.5
12.5
10.0
ns
ns
ns
ns
5.0
2.0
8.0
10.0
1.5
11.5
ns
5.0
2.5
8.5
11.0
2.0
11.5
ns
5.0
2.0
8.0
10.0
1.5
11.5
ns
5.0
Min
2.5
T
A
C
L
25
q
C
50 pF
Typ
8.5
Max
10.0
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
11.5
ns
Units
Min
1.5
Note 10:
Voltage Range 5.0 is 5.0V
r
0.5V
AC Operating Requirements for ACT
V
CC
Symbol
t
S
t
H
t
W
Parameter
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
5.0
2.0
7.0
8.0
ns
Note 11:
Voltage Range 5.0 is 5.0V
r
0.5V
T
A
C
L
Typ
0.8
0
25
q
C
50 pF
T
A
40
q
C to
85
q
C
C
L
50 pF
Units
ns
ns
(V)
(Note 11)
5.0
5.0
Guaranteed Minimum
2.5
0
3.5
1.0
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
40.0
Units
pF
pF
V
CC
V
CC
OPEN
5.0V
Conditions
5
www.fairchildsemi.com
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
